Ecosyste.ms: OpenCollective
An open API service for software projects hosted on Open Collective.
github.com/rizinorg/rz-hexagon
Hexagon disassembler code generator for Rizin from the official instruction manual.
https://github.com/rizinorg/rz-hexagon
Remove check for legal NULL condition and handle it.
Rot127 opened this pull request 9 months ago
Rot127 opened this pull request 9 months ago
Dup value string in hex_cfg_set()
pelijah opened this pull request 9 months ago
pelijah opened this pull request 9 months ago
Arch refactor + not imported changes
Rot127 opened this pull request 11 months ago
Rot127 opened this pull request 11 months ago
Fix token patterns for asm strings for PCRE2
Rot127 opened this pull request about 1 year ago
Rot127 opened this pull request about 1 year ago
Implement `analysis_preludes`/generate function prologues
Rot127 opened this issue about 1 year ago
Rot127 opened this issue about 1 year ago
Fix some resource leaks.
Rot127 opened this pull request about 1 year ago
Rot127 opened this pull request about 1 year ago
Add maxargs to Calling Convention
Rot127 opened this pull request about 1 year ago
Rot127 opened this pull request about 1 year ago
Obey `RZ_ANALYSIS_OP_MASK`
Rot127 opened this issue about 1 year ago
Rot127 opened this issue about 1 year ago
Generate Dwarf register number table.
Rot127 opened this pull request about 1 year ago
Rot127 opened this pull request about 1 year ago
Update to LLVM b6f51787f6c8e77143f0aef6b58ddc7c55741d5c
Rot127 opened this pull request over 1 year ago
Rot127 opened this pull request over 1 year ago
HMX extension
Rot127 opened this issue over 1 year ago
Rot127 opened this issue over 1 year ago
New instruction support
XVilka opened this issue almost 2 years ago
XVilka opened this issue almost 2 years ago
Tag release
Rot127 opened this issue almost 2 years ago
Rot127 opened this issue almost 2 years ago
Remove duplicate imported instructions
Rot127 opened this issue about 2 years ago
Rot127 opened this issue about 2 years ago
Generate plugin with instructions for Hexagon v71,v71t,v73.
Rot127 opened this pull request about 2 years ago
Rot127 opened this pull request about 2 years ago
Add missing type annotations
Rot127 opened this pull request over 2 years ago
Rot127 opened this pull request over 2 years ago
Add /*<type>*/ comments and fix annotation inconsistencies
wingdeans opened this pull request over 2 years ago
wingdeans opened this pull request over 2 years ago
Disassemble invalid duplex instructions to `invalid ; invalid`.
Rot127 opened this pull request over 2 years ago
Rot127 opened this pull request over 2 years ago
Replace `RzList HexPkt.bin` with `RzVector`
Rot127 opened this issue over 2 years ago
Rot127 opened this issue over 2 years ago
Color sub-instructons separately
Rot127 opened this issue over 2 years ago
Rot127 opened this issue over 2 years ago
Add asm-token code.
Rot127 opened this pull request over 2 years ago
Rot127 opened this pull request over 2 years ago
Remove generation of duplex instruction
Rot127 opened this pull request over 2 years ago
Rot127 opened this pull request over 2 years ago
Add missing reloc test.
Rot127 opened this pull request over 2 years ago
Rot127 opened this pull request over 2 years ago
Compare buffered opcodes to current one at the same address
Rot127 opened this issue over 2 years ago
Rot127 opened this issue over 2 years ago
Rename `HEX_OP_TEMPLATE_FLAG_IMM_DOUBLE_HASH`
Rot127 opened this issue over 2 years ago
Rot127 opened this issue over 2 years ago
Generate RZIL operations
Rot127 opened this pull request over 2 years ago
Rot127 opened this pull request over 2 years ago
Files are not written if they differ only in blank characters
Rot127 opened this issue over 2 years ago
Rot127 opened this issue over 2 years ago
Add CI linter checks
Rot127 opened this pull request over 2 years ago
Rot127 opened this pull request over 2 years ago
Replace Duplex instruction generation with sub-instruction focused approach
Rot127 opened this issue over 2 years ago
Rot127 opened this issue over 2 years ago
Setup CI
Rot127 opened this issue over 2 years ago
Rot127 opened this issue over 2 years ago
Virtual Python environment
Rot127 opened this issue over 2 years ago
Rot127 opened this issue over 2 years ago
#52 refactor tasks
Rot127 opened this pull request almost 3 years ago
Rot127 opened this pull request almost 3 years ago
Remove manually added intendations `"...".format(indent, ...)` (clang-format-13 does it)
Rot127 opened this issue almost 3 years ago
Rot127 opened this issue almost 3 years ago
Fail safely when too few bytes are provided to disasm
thestr4ng3r opened this pull request almost 3 years ago
thestr4ng3r opened this pull request almost 3 years ago
Generate instruction templates as C structs
thestr4ng3r opened this pull request almost 3 years ago
thestr4ng3r opened this pull request almost 3 years ago
RxIn registers have `REG_OUT` flag set.
Rot127 opened this issue almost 3 years ago
Rot127 opened this issue almost 3 years ago
Set constant -1 value and type in `hi->ops[]`.
Rot127 opened this pull request almost 3 years ago
Rot127 opened this pull request almost 3 years ago
Sort imported instruction/register files before processing.
Rot127 opened this pull request almost 3 years ago
Rot127 opened this pull request almost 3 years ago
Hexagon register profile
Rot127 opened this pull request almost 3 years ago
Rot127 opened this pull request almost 3 years ago
Easy way to keep `rz-hexagon` and `rizin` src in sync
Rot127 opened this issue almost 3 years ago
Rot127 opened this issue almost 3 years ago
Plugin config
Rot127 opened this pull request almost 3 years ago
Rot127 opened this pull request almost 3 years ago
Refactor: Remove code duplicates
Rot127 opened this pull request almost 3 years ago
Rot127 opened this pull request almost 3 years ago
Refactor code - tracker
Rot127 opened this issue almost 3 years ago
Rot127 opened this issue almost 3 years ago
Update register profile
Rot127 opened this pull request almost 3 years ago
Rot127 opened this pull request almost 3 years ago
Refresh timestamps only on code changes
Rot127 opened this pull request almost 3 years ago
Rot127 opened this pull request almost 3 years ago
Fix cid 367529
Rot127 opened this pull request about 3 years ago
Rot127 opened this pull request about 3 years ago
Add READMEs to describe import process.
Rot127 opened this pull request about 3 years ago
Rot127 opened this pull request about 3 years ago
Add Hexagon IDE conforming packet syntax
Rot127 opened this pull request about 3 years ago
Rot127 opened this pull request about 3 years ago
Hexagon v69
Rot127 opened this pull request about 3 years ago
Rot127 opened this pull request about 3 years ago
Analyse function preludes
Rot127 opened this issue about 3 years ago
Rot127 opened this issue about 3 years ago
`endloopX` jumps always jump to `loopX` start. Not to the value in the `SA` register.
Rot127 opened this issue about 3 years ago
Rot127 opened this issue about 3 years ago
Function argument passing incorrect.
Rot127 opened this issue about 3 years ago
Rot127 opened this issue about 3 years ago
Generate FLIRT signatures
Rot127 opened this issue about 3 years ago
Rot127 opened this issue about 3 years ago
Adapt basic block analysis for the Hexagon architecture.
Rot127 opened this pull request about 3 years ago
Rot127 opened this pull request about 3 years ago
endloop01 packets miss the third way of branching.
Rot127 opened this issue about 3 years ago
Rot127 opened this issue about 3 years ago
Add tests for string search in analysis.vals.
Rot127 opened this pull request about 3 years ago
Rot127 opened this pull request about 3 years ago
Write LLVM commit hash and date into header of source files
Rot127 opened this issue about 3 years ago
Rot127 opened this issue about 3 years ago
Implement get_reg_profile instead of set_reg_profile
thestr4ng3r opened this pull request about 3 years ago
thestr4ng3r opened this pull request about 3 years ago
Allow multiple `endloop` packets per loop instruction
Rot127 opened this issue about 3 years ago
Rot127 opened this issue about 3 years ago
Fix CID 365806 and refactor
Rot127 opened this pull request about 3 years ago
Rot127 opened this pull request about 3 years ago
Replace imported system registers with the LLVM generated one.
Rot127 opened this issue about 3 years ago
Rot127 opened this issue about 3 years ago
Add missing RZ_API in declaration.
Rot127 opened this pull request about 3 years ago
Rot127 opened this pull request about 3 years ago
Add ARCHITECTURE.md
Rot127 opened this issue about 3 years ago
Rot127 opened this issue about 3 years ago
Function analysis does not add complete packet to function.
Rot127 opened this issue about 3 years ago
Rot127 opened this issue about 3 years ago
Incorrect function recognition because of predicated jumps
Rot127 opened this issue over 3 years ago
Rot127 opened this issue over 3 years ago
No representation of predicates in rizin
Rot127 opened this issue over 3 years ago
Rot127 opened this issue over 3 years ago
Incorrect size of predicate registers in register profile
Rot127 opened this issue over 3 years ago
Rot127 opened this issue over 3 years ago
rizin tests
Rot127 opened this issue over 3 years ago
Rot127 opened this issue over 3 years ago
Import/Export symbol patching is missing
Rot127 opened this issue over 3 years ago
Rot127 opened this issue over 3 years ago
Duplex instructions: High instr. is printed before low instruction
Rot127 opened this issue over 3 years ago
Rot127 opened this issue over 3 years ago
Track the state and context of the asm and analysis plugin.
Rot127 opened this issue over 3 years ago
Rot127 opened this issue over 3 years ago
Add methods which wrap code into a c-block/function/switch-case
Rot127 opened this issue over 3 years ago
Rot127 opened this issue over 3 years ago
Add Doxygen documentation to functions
Rot127 opened this issue over 3 years ago
Rot127 opened this issue over 3 years ago
Easy way to import undocumented and missing instructions
Rot127 opened this issue over 3 years ago
Rot127 opened this issue over 3 years ago
Register sizes >256bit are not supported by rizin
Rot127 opened this issue over 3 years ago
Rot127 opened this issue over 3 years ago
Simpler search for negative immediates
Rot127 opened this issue over 3 years ago
Rot127 opened this issue over 3 years ago
Track instruction packet membership in more detail
Rot127 opened this issue over 3 years ago
Rot127 opened this issue over 3 years ago
Omit packet prefix if only one instruction is disassembled
Rot127 opened this issue over 3 years ago
Rot127 opened this issue over 3 years ago
Patches: rizin pull request
Rot127 opened this pull request over 3 years ago
Rot127 opened this pull request over 3 years ago
Disassemble 0x00000000 to <unknown>; not to a valid dublex instruction.
Rot127 opened this issue over 3 years ago
Rot127 opened this issue over 3 years ago
Set more RzAnalysisOp members
Rot127 opened this issue over 3 years ago
Rot127 opened this issue over 3 years ago
RzAnalysisOp.val won't get set
Rot127 opened this issue over 3 years ago
Rot127 opened this issue over 3 years ago
Instruction behavior as RZIL/p-code
Rot127 opened this issue over 3 years ago
Rot127 opened this issue over 3 years ago
Refactor parse_instruction()
Rot127 opened this issue over 3 years ago
Rot127 opened this issue over 3 years ago
Missing analysis tests
Rot127 opened this issue over 3 years ago
Rot127 opened this issue over 3 years ago
Syntax highlighting is broken
Rot127 opened this issue over 3 years ago
Rot127 opened this issue over 3 years ago
Add tests for HVX disassembly
Rot127 opened this issue over 3 years ago
Rot127 opened this issue over 3 years ago
Missing double control registers
Rot127 opened this issue over 3 years ago
Rot127 opened this issue over 3 years ago
Assign specific register types to HVX registers and control registers
Rot127 opened this issue over 3 years ago
Rot127 opened this issue over 3 years ago
SDB file with calling convnetion is not generated and outdated
Rot127 opened this issue over 3 years ago
Rot127 opened this issue over 3 years ago
LLVM replaces Manual
Rot127 opened this pull request over 3 years ago
Rot127 opened this pull request over 3 years ago
importer.py: Add gcc deoptimization attribute for Rizin CI ASAN build
kazarmy opened this pull request almost 4 years ago
kazarmy opened this pull request almost 4 years ago
Add support for post-v62 instructions as well as HVX
XVilka opened this issue about 4 years ago
XVilka opened this issue about 4 years ago
Compare results with other Hexagon disassemblers
XVilka opened this issue about 4 years ago
XVilka opened this issue about 4 years ago