github.com/llvm/circt issues | Ecosyste.ms: OpenCollective

[FIRRTL][LowerLayers] Update rwprobe operations if possible.

dtzSiFive opened this pull request 3 months ago

[ImportVerilog] Fix use after free

fzi-hielscher opened this pull request 3 months ago

[ESI runtime] Host memory service

teqdruid opened this pull request 3 months ago

[FIRRTL][Inliner][InstChoice] Basic example doesn't work

dtzSiFive opened this issue 3 months ago

[FIRRTL][LowerLayers] Cannot send rwprobe out of layer

dtzSiFive opened this issue 3 months ago

[firtool][test] Check layer specialization options work.

dtzSiFive opened this pull request 3 months ago

[ESI][Runtime] Publish Windows wheels

teqdruid opened this pull request 3 months ago

[MooreToCore] Support ProcedureOp and sequential assign operations

maerhart opened this pull request 3 months ago

[FIRRTL] Canonicalization missing for narrow dynamic subindex

uenoku opened this issue 3 months ago

[Arc] Add Initial Cost Model

elhewaty opened this pull request 3 months ago

[firtool] Make layer specialization take a list of layers

youngar opened this pull request 3 months ago

[FIRRTL] LowerToHW: guard against folded operations

youngar opened this pull request 3 months ago

[LLHD] Refactor llhd.proc and remove llhd.inst

maerhart opened this pull request 3 months ago

[Handshake] Fix library dependencies

youngar opened this pull request 3 months ago

[CI] Report failure of clang-tidy

rwy7 opened this pull request 3 months ago

[ESI] Separate data delay from signaling standard

teqdruid opened this pull request 3 months ago

[LLHD] Use hw.inout instead of llhd.sig

maerhart opened this pull request 3 months ago

[ESI Runtime] If zlib not found, use FetchContent

teqdruid opened this pull request 3 months ago

[LLHD] Remove llhd-sim

maerhart opened this pull request 3 months ago

[Seq] Canonicalize firreg with preset 0

prithayan opened this pull request 3 months ago

[ImportVerilog] Add basic function support

fabianschuiki opened this pull request 3 months ago

[FIRRTL] AssignOutputDirs: Ensure absolute dirs end with trailing slash

rwy7 opened this pull request 3 months ago

[FIRRTL] Incorrect Output Directory for Multiply Instantiate Module in Layer

seldridge opened this issue 3 months ago

[LowerToHW] Crash involving `TestBenchDirAnnotation`

seldridge opened this issue 3 months ago

[firtool] Not parsing enable/disable layers CLI option properly

youngar opened this issue 3 months ago

[MooreToCore] Support NegOp lowering

maerhart opened this pull request 3 months ago

[circt-bmc] Add LowerToBMC Pass

TaoBi22 opened this pull request 3 months ago

[FIRRTL][ProbesToSignals] Add pass to replace probes with signals.

dtzSiFive opened this pull request 3 months ago

[Moore] [Canonicalizer] Lower struct-related assignOp

mingzheTerapines opened this pull request 3 months ago

[Moore] Distinguish the dynamic and constant extract.

hailongSun2000 opened this pull request 3 months ago

[ImportVerilog] Allow enum variants in expressions

fabianschuiki opened this pull request 3 months ago

[ESI Runtime] Windows: python support and backend plugin loading

teqdruid opened this pull request 3 months ago

[ImportVerilog] Handle $signed/$unsigned system tasks

fabianschuiki opened this pull request 3 months ago

[ImportVerilog] Fix unbased unsized literals of packed aggregate type

fabianschuiki opened this pull request 3 months ago

[HW][SV] Transition "HWToSV" to "ProceduralCoreToSV" pass.

fzi-hielscher opened this pull request 3 months ago

[ImportVerilog] Accept empty packages

fabianschuiki opened this pull request 3 months ago

[ExportVerilog] Add "context" to imported DPI functions

uenoku opened this pull request 3 months ago

[PrepareForEmission][Prettify] Extend allowExprInClock to handle new verif ops

uenoku opened this pull request 3 months ago

[PyCDE] Bundles: coerce method

teqdruid opened this pull request 3 months ago

[PyCDE] Simple transforms on channels

teqdruid opened this pull request 3 months ago

[FIRRTL] Investigate LowerClasses namespace lifetimes

mikeurbach opened this issue 3 months ago

Reland "[FIRRTL][LowerClass] Pre-allocate namespaces before capturing refs (#7102)".

mikeurbach opened this pull request 3 months ago

[FIRRTL] Crash in LowerClasses related to StringMap buckets

mikeurbach opened this issue 3 months ago

[Moore] Add MergeExtractRef pass.

hailongSun2000 opened this pull request 3 months ago

[Verif] Introduce Formal Contracts

dobios opened this pull request 3 months ago

[FIRRTL] Feature Request: Have dedup report all errors, not just the first

debs-sifive opened this issue 3 months ago

[README] what does "IR" stand for?

parker-research opened this issue 3 months ago

[FIRRTL] Add lowering support for inline layers

rwy7 opened this pull request 3 months ago

[ImportVerilog] Tweak the implementation of for loops.

hailongSun2000 opened this pull request 3 months ago

[Scheduling] Replace macro use in problem definitions

jopperm opened this pull request 3 months ago

[CI] Drop macos-11 runners, use macos-12 in uploadReleaseArtifacts

jackkoenig opened this pull request 3 months ago

[llvm] Bump to 0870afaaaccde5b4bae37abfc982207ffafb8332

leonardt opened this pull request 3 months ago

[FIRRTL] Replace "noRefTypePorts" with Pass

seldridge opened this issue 3 months ago

[Sim] Flatten format string concatenations in canonicalizer

fzi-hielscher opened this pull request 3 months ago

[ESI] Remove last references to capnp

teqdruid opened this pull request 3 months ago

[HW][SV] Allow procedural SV ops in hw::TriggeredOp

fzi-hielscher opened this pull request 3 months ago

[Moore] Extend the operand of AssignOp and add PullNonBlockingUp pass.

hailongSun2000 opened this pull request 3 months ago

[OM] Introduce API to interact with class fields

leonardt opened this pull request 3 months ago

Revert "[FIRRTL] Enable Wire Elimination (#7073)"

jackkoenig opened this pull request 3 months ago

[ESI][PyCDE] ChannelSignal: add `buffer` method

teqdruid opened this pull request 3 months ago

Allow firrtl hardware ops under sv.ifdef

rwy7 opened this pull request 3 months ago

Perf measurements link (https://circt.org/perf/) broken

mgielda opened this issue 3 months ago

Main link on GH broken (circt.org rather than https://circt.llvm.org/)

mgielda opened this issue 3 months ago

[ESI] MMIO read service implementation in PyCDE

teqdruid opened this pull request 3 months ago

[FIRRTL][LowerDPI] Lower FIRRTL vector to an open array type

uenoku opened this pull request 3 months ago

[SV][ExportVerilog] Add UnpackedOpenArrayType, cast op and emission

uenoku opened this pull request 3 months ago

[SV] Add UnpackedArrayCreateOp

uenoku opened this pull request 3 months ago

[SV] Add Intermediary Assert Op for better enable polarity flip

dobios opened this pull request 3 months ago

Lower MemRef GetGlobal and write data to json files

jiahanxie353 opened this pull request 3 months ago

Move ResetType under the sv namespace

rwy7 opened this pull request 3 months ago

[PyCDE][ESI] Manifest: add record about client

teqdruid opened this pull request 3 months ago

Transform Flatten Memref Load

jiahanxie353 opened this pull request 3 months ago

[MooreToCore] Lower var, read, and assign into LLHD.

hailongSun2000 opened this pull request 3 months ago

[SV][Verif] Extract clocked verif ops in ExtractTestCode pass

uenoku opened this pull request 3 months ago

[ImportVerilog] Fix the segmentation fault caused by the case statement.

hailongSun2000 opened this pull request 3 months ago

[FIRRTL] Inconsistency when compiling two semantically equivalent fir code

JacyCui opened this issue 3 months ago

[HW] Specify llvm::SmallVector namespace. NFC.

prithayan opened this pull request 3 months ago

[Sim] Add printing operations and transformation from non-procedural to procedural flavor

fzi-hielscher opened this pull request 3 months ago

[NFC][HW] Fix parsing of nullary `hw.triggered` ops

fzi-hielscher opened this pull request 3 months ago

[Verif] Remove Verif dialect print/format operations

fzi-hielscher opened this pull request 3 months ago

[Seq] Remove incorrect canonicalization

uenoku opened this pull request 3 months ago

CODEOWNERS: remove @dtzSiFive from most paths.

dtzSiFive opened this pull request 3 months ago

[ESI] Add verify connections pass

teqdruid opened this pull request 3 months ago

[ESI] Add value validation to Channels and Bundles

teqdruid opened this issue 4 months ago

[circt-bmc] Add ExternaliseRegisters Pass

TaoBi22 opened this pull request 4 months ago

[Arc] Keep just one parameter if it's given multiple times

elhewaty opened this pull request 4 months ago

[ESI] Make MMIO data 64-bit

teqdruid opened this pull request 4 months ago

[ESI] Add read-side MMIO back

teqdruid opened this pull request 4 months ago

[SV] Add option to generate ram blocks without x assigns

hutch31 opened this issue 4 months ago

[ImportVerilog] Distinguish the index up or down on the range selection.

hailongSun2000 opened this pull request 4 months ago

[FIRRTL][ModuleInliner] Add a prefix to memory instances

uenoku opened this pull request 4 months ago

[Moore] SymbolVisibility attribute support for SVModuleOp

cepheus69 opened this pull request 4 months ago

[PyCDE] Restrict slicing index widths to clog2(len)

teqdruid opened this pull request 4 months ago

[FIRRTL] FART: Should not modify public module ports

youngar opened this issue 4 months ago

[FIRRTL] InferResets: extmodules should not be allowed to have abstract resets

youngar opened this issue 4 months ago

[FIRRTL] FART: when annotated reset is under a when, always leads to uninitialized wires

youngar opened this issue 4 months ago

[FIRRTL] Fix use-after-free in InferReset

darthscsi opened this pull request 4 months ago

[FIRRTL] Ensure hierpath considers owning module in LowerClasses.

mikeurbach opened this pull request 4 months ago

[FIRRTL] FART: logic to reuse existing port can result in the wrong reset

youngar opened this issue 4 months ago

[FIRRTL] FullAsynchronousResetTransform should be moved out of InferResets

youngar opened this issue 4 months ago