github.com/llvm/circt issues | Ecosyste.ms: OpenCollective

Add the BLIF dialect.

darthscsi opened this pull request 6 days ago

[CombToAIG] Lower comb.icmp

uenoku opened this pull request 10 days ago

[CombToAIG] Add a pattern for mul

uenoku opened this pull request 10 days ago

[Comb] delete slow canonicalizer

youngar opened this pull request 11 days ago

[LLHD] Canonicalizer for processes produced by always @(*)

maerhart opened this issue 12 days ago

[Moore][Arc][LLHD] Moore to LLVM lowering issues

likeamahoney opened this issue 14 days ago

[PyCDE] Add fork, join, and merge channel functions

teqdruid opened this pull request 15 days ago

[ImportVerilog] Support for Procedural assign statements

owlxiao opened this pull request 15 days ago

[ESI] FIFO: support valid/ready on inputs and outputs

teqdruid opened this pull request 16 days ago

[PyCDE] Update build flow

teqdruid opened this pull request 16 days ago

[LowerToBMC] Topologically sort module body before inlining to BMC op

TaoBi22 opened this pull request 16 days ago

[VerifToSMT] Fix incorrect loop region result indexing

TaoBi22 opened this pull request 16 days ago

[CD] Install nanobind when building wheels.

mikeurbach opened this pull request 17 days ago

[ESI] FIFO with ESI channels

teqdruid opened this pull request 17 days ago

[Seq] Fix FIFO lowering to correct depth and pointer increments

teqdruid opened this pull request 17 days ago

[Seq] Counters

teqdruid opened this issue 17 days ago

[FIRRTL] Support MarkDUTAnnotation on extmodules.

mikeurbach opened this pull request 17 days ago

CIRCT Regression tests Failed in nixpkgs

unlsycn opened this issue 17 days ago

[ImportVerilog] sva prototype

chenbo-again opened this pull request 18 days ago

[RTG][Elaboration] Move ConstantLike check after TypeSwitch for better performance

maerhart opened this pull request 18 days ago

[RTG][Elaboration] Do not internalize primitive values

maerhart opened this pull request 18 days ago

Bug Report: Property string with quote parse failed

sequencer opened this issue 19 days ago

[firtool] initialize the disableLayerSink flag

youngar opened this pull request 20 days ago

[Firtool][CAPI] Valgrind failure re: shouldDisableLayerSink

seldridge opened this issue 20 days ago

[SCFToCalyx] Add indent size annotation when writing json files

jiahanxie353 opened this pull request 21 days ago

[FIRRTL] IMDCE: not removing all dead instances

youngar opened this issue 21 days ago

[HW] Add pass to outline certain ops: hw-outline-ops

teqdruid opened this pull request 21 days ago

[FIRRTL] better wire canonicalization

youngar opened this issue 21 days ago

[LLHD] Improve llhd-desequentialize pass

AndreyVV-100 opened this issue 21 days ago

[InstanceChoice] Move specialize options pass earlier in the firtool pipeline

prithayan opened this pull request 21 days ago

[InstanceChoice][FIRRTL] Ensure instance graph can handle InstanceChoiceOp

prithayan opened this issue 21 days ago

[RTG][Elaboration] Add support for 'scf.if' and 'scf.for'

maerhart opened this pull request 21 days ago

[LLHD] Fix misprint in llhd-desequentialize pass

AndreyVV-100 opened this pull request 21 days ago

Build and test LLVM/MLIR Failed

quanchenliu opened this issue 22 days ago

[FIRRTL] Use PRINTF_FD macro instead of 0x80000002 as printf fd

Clo91eaf opened this pull request 22 days ago

[FIRRTL] AdvancedLayerSink: don't sink instances of mods with port annos

rwy7 opened this pull request 22 days ago

[firtool] Add option to disable layer sink

youngar opened this pull request 22 days ago

[SCFToCalyx] Fix json naming when there are multiple components

jiahanxie353 opened this pull request 22 days ago

[RTG] Add InstructionOpInterface

maerhart opened this pull request 22 days ago

[RTG][Elaboration] Add support for 'index.add' and 'index.cmp'

maerhart opened this pull request 22 days ago

[SCFToCalyx] buildLibraryOp cast floating point to integer types

jiahanxie353 opened this pull request 22 days ago

Bump LLVM to b0b546d44777eb1fa25995384876bd14a006a929.

mikeurbach opened this pull request 22 days ago

Fix warnings about unused variables when assertions are disabled (NFC)

maerhart opened this pull request 22 days ago

[circt-bmc] Add option to print solver output & assertions

TaoBi22 opened this pull request 22 days ago

[Do-Not-Merge][FIRRTL][Sim][SV] Rework `printf` lowering pipeline

fzi-hielscher opened this pull request 22 days ago

Re-land: [FIRRTL][CAPI] Add more functions for discriminating and querying type

SpriteOvO opened this pull request 22 days ago

[ImportVerilog] Support for sized unpacked arrays in 'inside' expressions

ladisgin opened this pull request 23 days ago

[CAPI] Windows and Nightly Failure after #7960

seldridge opened this issue 23 days ago

[RTG][Elaboration] Support sequences

maerhart opened this pull request 23 days ago

[CombToAIG] Add a lowering for Add/Sub

uenoku opened this pull request 24 days ago

[CombToAIG] Add a pattern for lowering varidaic operations

uenoku opened this pull request 24 days ago

[CombToAIG] Add mux lowering

uenoku opened this pull request 24 days ago

[OM] Generalize handling for list creation ops in FreezePaths.

mikeurbach opened this pull request 24 days ago

[RTG] Add operation and types to represent labels

maerhart opened this pull request 24 days ago

[LLHD] Segmentation fault in Desequentialization Pass

AndreyVV-100 opened this issue 24 days ago

[llvm] Revert LLVM de-bump

seldridge opened this pull request 25 days ago

[HWArith] Lowering to HW with type aliases

teqdruid opened this issue 25 days ago

[FIRRTL][CAPI] Add more functions for discriminating and querying type

SpriteOvO opened this pull request 27 days ago

Fix temporal code motion

AndreyVV-100 opened this pull request 28 days ago

[ci] Valgrind builds failed in Slang

seldridge opened this issue 28 days ago

FIRRTL memory read-under-write is not respected

programmerjake opened this issue 28 days ago

[SCFToCalyx] replace shell command with %T for Windows in the test file

jiahanxie353 opened this pull request 29 days ago

[InstanceChoice] Add a default override for unspecified options

prithayan opened this pull request 29 days ago

[SCFToCalyx] replace shell command with %S for Windows in the test file

jiahanxie353 opened this pull request 29 days ago

[SCFToCalyx] `memref::getGlobalOp` write to json using explicit toString for path to fix Windows failed test

jiahanxie353 opened this pull request 29 days ago

[DC] Add + re-enable canonicalization patterns

mortbopet opened this pull request 29 days ago

[FirParser] Add instance choice selection as circt attribute

prithayan opened this pull request 29 days ago

[SMT] Require SolverOp parent for SetLogicOp

TaoBi22 opened this pull request 29 days ago

[DCToHW] Pass creates invalid ESI connections

teqdruid opened this issue 30 days ago

[LowerTypes] Copy discardable attributes when cloning operations

uenoku opened this pull request 30 days ago

[ExportVerilog] Fix ifdef of macro w/ Verilog name

seldridge opened this pull request 30 days ago

[FIRRTL] Clock gate extraction work w/ prefixing

seldridge opened this pull request 30 days ago

[DC] Initial values were being ignored

teqdruid opened this pull request 30 days ago

[FIRRTL] Remove NestedPrefixModulesAnnotation

seldridge opened this pull request about 1 month ago

[MooreToCore] Add multibit DetectEventOp support

AndreyVV-100 opened this pull request about 1 month ago

[Arc] Introduce a Python simulation script generator for arcilator

gtxzsxxk opened this issue about 1 month ago

[CombToAIG] Populate legal ops

uenoku opened this pull request about 1 month ago

[RTG] Generate separate doc files for ops and types

maerhart opened this pull request about 1 month ago

[HWToBTOR2] Generate register initial constant before state declaration

TaoBi22 opened this pull request about 1 month ago

[ESI] Attribute documentation not rendered correctly

maerhart opened this issue about 1 month ago

[AIG] Pass documentation rendered incorrectly

maerhart opened this issue about 1 month ago

[DC] Add unused fork result elimination canonicalizer

teqdruid opened this pull request about 1 month ago

[Verilog][FIRRTL] Improve `$signed` Elision

seldridge opened this issue about 1 month ago

[firtool] `firrtl.AttributeAnnotation` on arrays is ignored by firtool

kammoh opened this issue about 1 month ago

[InstanceChoice] Add the instance choice specialization pass to firtool

prithayan opened this pull request about 1 month ago

[RTG] broken documentation

youngar opened this issue about 1 month ago

[firtool] Add an option to disable CSE in classes

prithayan opened this pull request about 1 month ago

[SMT] Add Z3 lowering for set_logic op

TaoBi22 opened this pull request about 1 month ago

[Arc] Refactor C++ header generator script to use Jinja templates

gtxzsxxk opened this pull request about 1 month ago

[ImportVerilog] Add case inside

ankolesn opened this pull request about 1 month ago

[SMT] Add set_logic operation

TaoBi22 opened this pull request about 1 month ago

[Calyx] Avoid using designated initializers

TaoBi22 opened this pull request about 1 month ago

[MooreToCore] LSB and MSB support in moore dialect

AndreyVV-100 opened this issue about 1 month ago

[RTGTest] Add some registers

maerhart opened this pull request about 1 month ago

[VerifToSMT] Exit early after too many clocks error

TaoBi22 opened this pull request about 1 month ago

[circt-bmc] Add a simple test with a register storing an aggregate

maerhart opened this pull request about 1 month ago

[RTG] Elaboration support for set_size and bag_unique_size operations

maerhart opened this pull request about 1 month ago

[RTG] Add set_size op for sets and bag_unique_size op for bags

maerhart opened this pull request about 1 month ago

Fix URL for firrtl spec

sequencer opened this pull request about 1 month ago

[MooreToCore] `moore.extract` is converted to `hw.array_slice` when array's element type is also array

slowlime opened this issue about 1 month ago