github.com/llvm/circt issues | Ecosyste.ms: OpenCollective

[ExportVerilog] Do not inline non-procedural continuous assignments to variables

fzi-hielscher opened this pull request about 2 months ago

[FIRRTL] Dedup: record less indices when hashing

youngar opened this pull request about 2 months ago

[FIRRTL] Dedup: speed up handling of instances

youngar opened this pull request about 2 months ago

[firtool] Run CSE on classes

youngar opened this pull request about 2 months ago

[FIRRTL] Accept list of parameters for `formal` construct

fabianschuiki opened this pull request about 2 months ago

[Handshake] Adding func instance op for integration

teqdruid opened this pull request about 2 months ago

[FIRRTL] Document how to deal with specification releases

fabianschuiki opened this pull request about 2 months ago

[Seq] FIFO: permit any type and add read latency

teqdruid opened this pull request about 2 months ago

[FIRRTL] Move LowerLayers after ExtractInstances

seldridge opened this pull request about 2 months ago

[FIRRTL] Bump nextFIRVersion to 4.0.0 in the parser

fabianschuiki opened this pull request about 2 months ago

[FIRRTL] Add layer support to ExtractInstances

seldridge opened this pull request about 2 months ago

[PyCDE] Binding for FIFOs

teqdruid opened this pull request about 2 months ago

Revert "[FIRRTL] Don't force non-local trackers in Dedup."

mikeurbach opened this pull request about 2 months ago

[Transform] Create memory banks for memories used inside affine parallel loops

jiahanxie353 opened this pull request about 2 months ago

[ESI] Implement basic hostmem reads lacking a bunch of functionality

teqdruid opened this pull request about 2 months ago

[FIRRTL] FIRParser: Speed up creation subaccess operations

youngar opened this pull request about 2 months ago

[ImportVerilog] How to implement SVA in Moore?

chenbo-again opened this issue about 2 months ago

[FIRRTL] Remove backwards compatibility flag in Dedup

mikeurbach opened this issue about 2 months ago

[FIRRTL] Only add SiTest metadata for design

seldridge opened this pull request about 2 months ago

[FIRRTL] Only emit retime metadata for design

seldridge opened this pull request about 2 months ago

[comb] Missing ~(~foo) canonicalization when foo is defined in another region

rwy7 opened this issue about 2 months ago

[FIRRTL] Run canonicalizer again after IMCP

rwy7 opened this pull request about 2 months ago

[ESI][Runtime] Fix wheel builds

teqdruid opened this pull request about 2 months ago

[firtool] mv LoweLayers after CreateSiFiveMetadata

seldridge opened this pull request about 2 months ago

[FIRRTL] InferRW: copy all attributes of masked memeories

youngar opened this pull request about 2 months ago

[ImportVerilog] Bump `slang`

hovind opened this pull request about 2 months ago

[SMT] Add reset op

TaoBi22 opened this pull request about 2 months ago

[CAPI][Python][Arc, HW] Register Arc and HW passes

yassinz opened this pull request about 2 months ago

[FIRRTL] Make memory matadata work with layers

seldridge opened this pull request about 2 months ago

ModulePrefixAnnotation not working properly on aggregate-typed cmems

jackkoenig opened this issue about 2 months ago

[circt-verilog] Support MLIR and MLIRBC input files

fabianschuiki opened this pull request about 2 months ago

[SMT] How to go from Verilog to smtlib2 like with Yosys?

flaviens opened this issue about 2 months ago

[FIRRTL] Emitting EICG wrapper warning only once

prithayan opened this pull request about 2 months ago

[ImportVerilog] add stream concat operation

chenbo-again opened this pull request about 2 months ago

[Moore] Add explicit truncation and zero/sign-extension

fabianschuiki opened this pull request about 2 months ago

[HW] Add a verifier for HWInstanceLike

prithayan opened this pull request about 2 months ago

[FIRRTL] infer more return types in asm format

youngar opened this pull request about 2 months ago

[firtool] Run layer merge after inliner

rwy7 opened this pull request about 2 months ago

[FIRRTL] Return an empty ArrayRef<Attr>, not an array of 1 attr

rwy7 opened this pull request about 2 months ago

[FreezePaths] Add support for HWInstanceLike, instead of only HWInstanceOp

prithayan opened this pull request about 2 months ago

[HW] Make module's doNotPrint a UnitAttr

rwy7 opened this pull request about 2 months ago

[FIRRTL] ReplSeqMems: use the original mem name for the instance name

youngar opened this pull request 2 months ago

[ESI][Services] Standard host memory service

teqdruid opened this pull request 2 months ago

[ESI][Services] Type comparisons should account for 'any'

teqdruid opened this pull request 2 months ago

[FIRRTL] Parser Accepts Duplicated Names Under Layerblock

seldridge opened this issue 2 months ago

[FIRRTL] Add new ModulePrefixAnnotation

youngar opened this pull request 2 months ago

[Draft] [OpLib] Create a Dialect for Representing Operator Libraries

andrewb1999 opened this pull request 2 months ago

[Calyx] constant op

jiahanxie353 opened this pull request 2 months ago

[Calyx] Binary Floating Point MulF Operator

jiahanxie353 opened this pull request 2 months ago

[SV] Use SymbolOpUserInterface to speed up verifiers

youngar opened this pull request 2 months ago

[HW] InnerSymbolTable: only check top-level ops for portlists

youngar opened this pull request 2 months ago

[FIRRTL] use properties in some builders and parsers

youngar opened this pull request 2 months ago

[FIRRTL] Make `sym_name` an inherent attr for symbol ops

youngar opened this pull request 2 months ago

[Calyx] Copy attributes when creating new top level function

jiahanxie353 opened this issue 2 months ago

[circt-test] Add simple runner interface for choosing modes and depth

leonardt opened this pull request 2 months ago

[Calyx] Sequential memory support floating point operations

jiahanxie353 opened this pull request 2 months ago

Use getDiscardableAttr to access discardable attributes

rwy7 opened this pull request 2 months ago

[FIRRTL] Fix folding of when conditions into LTL properties

fabianschuiki opened this pull request 2 months ago

[LTL] Canonicalize ltl.and to comb.and for i1 properties

fabianschuiki opened this pull request 2 months ago

Flatten memref Global and its corresponding GetGlobal operations

jiahanxie353 opened this pull request 2 months ago

[HW] Add port name accessors to HWInstanceLike

maerhart opened this pull request 2 months ago

[circt-test] Add simple SymbiYosys test runner

fabianschuiki opened this pull request 2 months ago

[circt-test] Add test discovery classes and `-l` option

fabianschuiki opened this pull request 2 months ago

[Verif][NFC] Use auto-generated constructors for all passes

fabianschuiki opened this pull request 2 months ago

[circt-verilog] zero parameter at module declaration fails when used

dacsson opened this issue 2 months ago

[MooreToCore] Add support for moore::string_constant #7628

jpinot opened this pull request 2 months ago

[FIRRTL] Add a new FIRRTL annotation to specify type lowering behavior of module body

uenoku opened this pull request 2 months ago

[FIRRTL] enable properties for inherent attributes

youngar opened this pull request 2 months ago

Bump LLVM to 8193832fb988e3df1e8e726634783805dca8d9b6.

mikeurbach opened this pull request 2 months ago

[OM] Add a new API to update fields of a ClassOp

prithayan opened this pull request 2 months ago

[FIRRTL] Remove validation from type inference code

youngar opened this pull request 2 months ago

[OM] Add ClassOp region verifier

seldridge opened this pull request 2 months ago

[Verif] Adjust contract ops to match documentation

fabianschuiki opened this pull request 2 months ago

[circt-lec] Register Verif dialect

uenoku opened this pull request 2 months ago

[AIG] Add CutOp

uenoku opened this pull request 2 months ago

[AIGToComb] [circt-synth] Add a AIG to Comb conversion pass

uenoku opened this pull request 2 months ago

[circt-synth] Populate pipelines until AIG lowering

uenoku opened this pull request 2 months ago

[CombToAIG] Add CombToAIG conversion pass

uenoku opened this pull request 2 months ago

[AIG] Add LowerVariadic and LowerWordToBits passes

uenoku opened this pull request 2 months ago

[AIG] Add AndInverterOp

uenoku opened this pull request 2 months ago

[AIG][circt-synth] Add a boilarplate for the dialect and tool

uenoku opened this pull request 2 months ago

Use properties for attributes for many dialects

youngar opened this pull request 2 months ago

[OM] Missing Verifier on Class Op return Type

seldridge opened this issue 2 months ago

[FIRRTL] clean up interfaces for supporting properties

youngar opened this pull request 2 months ago

Reject '<=' and 'is invalid' if FIRRTL version >=3

seldridge opened this pull request 2 months ago

[FIRRTL] Can't Parse Regreset w/ Self Connection

seldridge opened this issue 2 months ago

[FIRRTL] Remove FIRRTL 3.0.0 syntax Parsing

seldridge opened this issue 2 months ago

[FIRRTL] Invalidate syntax cannot invalidate an instance

seldridge opened this issue 2 months ago

[circt-bmc] Add initial_values attribute to BMC op

TaoBi22 opened this pull request 2 months ago

[circt-bmc] Add simple initial value support to ExternalizeRegisters

TaoBi22 opened this pull request 2 months ago

[HWToSMT] Proper error message for 0-bit constants

maerhart opened this pull request 2 months ago

[Comb] i0 in concat is not folded

uenoku opened this issue 2 months ago

[HWToSMT] Assertion failure on i0 constant

uenoku opened this issue 2 months ago

[FIRRTL][LayerSink] Fix: initialize an unitialized bool member

rwy7 opened this pull request 2 months ago

[Verif] Add contract examples to dialect doc

fabianschuiki opened this pull request 2 months ago

[FIRRTL] Canonicalizer erases empty bundle connection

uenoku opened this issue 2 months ago

[LowerToHW] Failure when lowering bundle_create which contains zero bit

uenoku opened this issue 2 months ago

[FIRRTL] Use InstanceInfo in CreateSiFiveMetadata

seldridge opened this pull request 3 months ago

[Verif] Add ignore attribute to formal

leonardt opened this pull request 3 months ago

[HW][Seq] Allow typed attr to be an element of aggregate_constant and make seq.const_clock typed attr

uenoku opened this pull request 3 months ago