github.com/llvm/circt issues | Ecosyste.ms: OpenCollective

Support `scf.if` Op Lowering to Calyx

jiahanxie353 opened this pull request over 1 year ago

[Seq] Add optional power-on value to `compreg` ops

mortbopet opened this pull request over 1 year ago

[Comb] Disallow canonicalization across MLIR blocks

mortbopet opened this pull request over 1 year ago

[FIRRTL] FirRegLowering mux-to-if conversion check could be more performant

mikeurbach opened this issue over 1 year ago

[Ibis] Add handshake to DC conversion

mortbopet opened this pull request over 1 year ago

[Ibis] Fix issues in Tunneling and PortRef lowering

mortbopet opened this pull request over 1 year ago

[Ibis] Fix clean selfdrivers in case of external reads

mortbopet opened this pull request over 1 year ago

test: Add some defensive FileCheck options.

dtzSiFive opened this pull request over 1 year ago

[Pipeline] Remove internal clock, reset,stall signals.

mortbopet opened this pull request over 1 year ago

[Ibis] Allow tunneling from `hw.module`s

mortbopet opened this pull request over 1 year ago

[Ibis] Print offending port name and use count on containers-to-hw error

blakep-msft opened this pull request over 1 year ago

[Ibis] Add Ibis CF to Handshake conversion

mortbopet opened this pull request over 1 year ago

[HW] Align instance_like_impl verification with `getReferencedModule`

mortbopet opened this pull request over 1 year ago

[NFC][ExportVerilog] Move location emission functions to class

mortbopet opened this pull request over 1 year ago

[Ibis] Allow multiple return values for `ibis.method`

mortbopet opened this pull request over 1 year ago

[NFC][Handshake] Adjust handshake interface defs and file locs

mortbopet opened this pull request over 1 year ago

[Handshake] Allow handshake ops to be used outside of a `handshake.func`

mortbopet opened this pull request over 1 year ago

[Ibis] Rename `ibis.block` -> `ibis.sblock`

mortbopet opened this pull request over 1 year ago

[HW] Support parametric UnpackedArrayType in hw-specialize

mortbopet opened this pull request over 1 year ago

[Pipeline] Fix issue in ExplicitRegs

mortbopet opened this pull request over 1 year ago

[Ibis] Add ibis reblock pass

mortbopet opened this pull request over 1 year ago

[Transforms] Move generally applicable passes to transforms

mortbopet opened this pull request over 1 year ago

[firtool] Run canonicalizer before LowerTypes

uenoku opened this pull request over 1 year ago

[Ibis] Add `--ibis-argify-blocks` pass

mortbopet opened this pull request over 1 year ago

[Seq] Add shiftreg op

mortbopet opened this pull request over 1 year ago

[SV] Fix --hw-eliminate-inout-ports

mortbopet opened this pull request over 1 year ago

Enable default builders for pipeline.LatencyOp

blakep-msft opened this pull request over 1 year ago

[HW] Use properties to store inherent attributes in HW ops.

dtzSiFive opened this pull request over 1 year ago

[Ibis] Add ibis.schedule op

mortbopet opened this pull request over 1 year ago

[Pipeline] valid -> enable

mortbopet opened this pull request over 1 year ago

[sifive-1.5] Bump workflows from ubuntu-18.04 to 20.04

jackkoenig opened this pull request over 1 year ago

[NFC] Don't directly poke location attributes from FlattenIO.cpp

darthscsi opened this pull request over 1 year ago

[Calyx] Add calyx.undef

rachitnigam opened this pull request over 1 year ago

[HW] HWModules don't implement FunctionOpInterface

darthscsi opened this pull request over 1 year ago

[Pipeline] Propagate names in `-pipeline-explicit-regs`

mortbopet opened this pull request over 1 year ago

[SV] Add suffix options to --hw-eliminate-inout-ports

mortbopet opened this pull request over 1 year ago

[Ibis] Add container-to-HW lowering pass

mortbopet opened this pull request over 1 year ago

[NFC] Add a Module Signature Converter which operates on HWModuleLike not FunctionOpInterface

darthscsi opened this pull request over 1 year ago

[NFC] Make FIRRTL modules not implement hwmodulelike

darthscsi opened this pull request over 1 year ago

[Transform] Initialize a new pass - GenStateStruct pass in Transform

cepheus69 opened this pull request over 1 year ago

[SV] Initialize a new pass - SVTriggerAttrGen pass in SV Transform

cepheus69 opened this pull request over 1 year ago

[HW/Support] Introduce InstanceGraph interface

mortbopet opened this pull request over 1 year ago

[Seq] Add FirRom op

vowstar opened this pull request over 1 year ago

Abstract out PortList from HWModuleLike

darthscsi opened this pull request over 1 year ago

New Module Parse Style

darthscsi opened this pull request over 1 year ago

[NFC] factor out port printing

darthscsi opened this pull request over 1 year ago

ExportVerilog emits ports preserving their order.

darthscsi opened this pull request over 1 year ago

Passes

MuhammadTalha-10 opened this issue over 1 year ago

[NFC] Use ModuleType to compute many properties

darthscsi opened this pull request over 1 year ago

[DC] `dc.value` should only take one type

mortbopet opened this pull request over 1 year ago

[NFC] change ModulePortInfo to store in a single array and get rid of redundant APIs. This is preparation for not splitting inputs and outputs.

darthscsi opened this pull request over 1 year ago

[DC] Add cast to/from ESI ops

mortbopet opened this pull request over 1 year ago

[NFC] Move functions from HWMutableModuleLike to HWModuleLike

darthscsi opened this pull request over 1 year ago

[Docs] Update dialects.dot for LoopSchedule

andrewb1999 opened this pull request over 1 year ago

[Seq] Add FIFO lowering

mortbopet opened this pull request over 1 year ago

[Verif] Add `format_verilog_string, print` operations

mortbopet opened this pull request over 1 year ago

[FIRRTL][LowerTypes] Consistently use 64bit for fieldID attr.

dtzSiFive opened this pull request over 1 year ago

[Pipeline] Allow explicitly named registers and passthroughs

mortbopet opened this pull request over 1 year ago

[SCFToCalyx] Use sequential memories

andrewb1999 opened this pull request over 1 year ago

[FIRRTL][LowerToHW] Zero-width signals with inner symbol are silently deleted, breaking users

dtzSiFive opened this issue over 1 year ago

[HW] Add `hw.triggered` op

mortbopet opened this pull request over 1 year ago

[Pipeline] Add missing name arg to builder

mortbopet opened this pull request over 1 year ago

[PipelineToHW] Don't CE pipeline regs in non-stallable pipelines

mortbopet opened this pull request over 1 year ago

[FIRRTL][InferResets] Should report nicely when a synchronous reset is annotated with FullAsyncResetAnnotation

rwy7 opened this issue over 1 year ago

[ExportVerilog] Missing `hw.struct_explode` support?

7FM opened this issue over 1 year ago

[Calyx] Add sequential memories

andrewb1999 opened this pull request over 1 year ago

[Seq] Unify `seq`-dialect memory representations

mortbopet opened this issue over 1 year ago

[FIRRTL][InferWidths] Back-prop for mux selector operand; different than subaccess

dtzSiFive opened this issue over 1 year ago

[HW/SV] Add `hw.inout` elimination pass

mortbopet opened this pull request over 1 year ago

[Pipeline] Add verifiers and fix register materialization pass

mortbopet opened this pull request over 1 year ago

[FIRRTL] Add string concatenation operation

youngar opened this pull request over 1 year ago

[Calyx] Add Static Groups and Control

andrewb1999 opened this pull request over 1 year ago

[Pipeline] Add "ext" inputs to pipelines

mortbopet opened this pull request over 1 year ago

[DCToHW] Add DCToHW conversion pass

mortbopet opened this pull request over 1 year ago

Update GettingStarted.md

flippers2652 opened this pull request over 1 year ago

circt-opt round-trip support (+add to CI?)

dtzSiFive opened this issue over 1 year ago

Add LTL and Verif dialects

fabianschuiki opened this pull request over 1 year ago

[FIRRTL] Introduce notation of discardable annotation

uenoku opened this pull request over 1 year ago

[HandshakeToDC] Add conversion

mortbopet opened this pull request over 1 year ago

[DC] Add merge operation

mortbopet opened this pull request over 1 year ago

[DC] Address canonicalizer review comments

mortbopet opened this pull request over 1 year ago

[FIRRTL] CAPI Additions

eigenform opened this pull request over 1 year ago

[DC] Add fork/sink materialization passes

mortbopet opened this pull request over 1 year ago

[FIRRTL] Bump minimum to 2.0.0, remove partial connect

seldridge opened this pull request over 1 year ago

[Dedup] Vector of bundles, with different field names should dedup

prithayan opened this issue over 1 year ago

Verilog frontend integration

fabianschuiki opened this pull request over 1 year ago

[Handshake] Remove handshake.select

mortbopet opened this pull request over 1 year ago

[FIRRTL] Support rwprobe that targets a port.

dtzSiFive opened this issue over 1 year ago

[FIRRTL] lower plusargs to initial block

darthscsi opened this pull request over 1 year ago

[FIRRTL] Lower complex enum to hw

darthscsi opened this pull request over 1 year ago

[FIRRTL] Enum tag extraction op

darthscsi opened this pull request almost 2 years ago

[LoopSchedule] Move PipelineWhile and related ops from Pipeline to LoopSchedule

andrewb1999 opened this pull request almost 2 years ago

[FIRRTL] InferResets Not Duplicating Modules When Necessary

jackkoenig opened this issue almost 2 years ago

How to avoid Unhandled annotation in Chisel-CIRCT

LandonWong opened this issue almost 2 years ago

[FIRRTL] Merge constants in concatinations and drop double inversion

darthscsi opened this pull request almost 2 years ago

[FIRRTL] Narrow And, Or, and Xor

darthscsi opened this pull request almost 2 years ago

[FIRRTL] prune duplicate conditions from mux trees

darthscsi opened this pull request almost 2 years ago

[FIRRLT] Narrow adds

darthscsi opened this pull request almost 2 years ago

[SV] Added DPI import and call ops

nandor opened this pull request almost 2 years ago

[Arc] A proposal about Arc simulation

cepheus69 opened this issue almost 2 years ago