github.com/llvm/circt issues | Ecosyste.ms: OpenCollective

[Seq] Allow presets for more types on firreg

nandor opened this pull request 10 months ago

[SV] Verify macro reference symbols

nandor opened this pull request 10 months ago

[SV] Emit macro declarations for all referenced macros

nandor opened this issue 10 months ago

[Sim] Emit a SYNTHESIS macro declaration if needed

nandor opened this pull request 10 months ago

[SV] Use a symbol in macro identifiers

nandor opened this pull request 10 months ago

[ImportVerilog] Make AST traveral non-recursive

fabianschuiki opened this issue 10 months ago

[FIRRTL] Memories incorrectly placed in testbench directory

seldridge opened this issue 10 months ago

[capi][python] Add Emit Dialect

seldridge opened this pull request 10 months ago

[ImportVerilog] Add assignment statements

fabianschuiki opened this pull request 10 months ago

[FIRRTL] Parser is using lookupSymbol when it could compute a SymbolTable once and re-use it.

mikeurbach opened this issue 10 months ago

[FIRRTL] Use the class map in ObjectOp parser.

mikeurbach opened this pull request 10 months ago

[FIRRTL] Handle reference ports when Classes dedup.

mikeurbach opened this pull request 10 months ago

[Calyx] Fix memory import locations

andrewb1999 opened this pull request 10 months ago

[RFC] [Comb][Canonicalize] Best effort dialect attribute propagation

7FM opened this pull request 10 months ago

[Comb][Canonicalize] Missing best effort dialect attribute propagation

7FM opened this issue 10 months ago

[ImportVerilog] Convert initial/always/final procedures

fabianschuiki opened this pull request 10 months ago

[Calyx] Switch sequential memories to be true single port memories

andrewb1999 opened this pull request 10 months ago

[ESI] Move entirely over to the runtime for testing

teqdruid opened this pull request 10 months ago

[ESI][Runtime] Build and publish wheels

teqdruid opened this pull request 10 months ago

[Emit] Introduce `emit.ref` to pull ops into file bodies

nandor opened this pull request 10 months ago

[WireDFT] Remove WireDFT

nandor opened this pull request 10 months ago

Support: Edge-Filtered Graph

dtzSiFive opened this pull request 10 months ago

[ESI][Runtime] Building wheels

teqdruid opened this pull request 10 months ago

[ExtractInstances] Fix Windows CI

nandor opened this pull request 10 months ago

[HW] Remove the file list attribute from HW

nandor opened this pull request 11 months ago

[Emit] Convert the ExtractInstances pass to use file ops

nandor opened this pull request 11 months ago

[ImportVerilog] Add type conversion and basic variables

fabianschuiki opened this pull request 11 months ago

[HW to BTOR2] Add support for initial values

Dobios opened this pull request 11 months ago

[HGLDD] Uniquify object names during emission

fabianschuiki opened this pull request 11 months ago

[FIRRTL] Generate filelist for each public module

tymcauley opened this issue 11 months ago

[MSFT][Emit] Replace `output_file` with an `emit::File`

nandor opened this pull request 11 months ago

[HGLDD] Fix instance output port emission

fabianschuiki opened this pull request 11 months ago

[HGLDD] Uniquify object names during emission

fabianschuiki opened this issue 11 months ago

[FIRRTL] Correct bindfile output for layers

rwy7 opened this issue 11 months ago

[FIRRTL][FIRParser] Enforce 4.0.0 main module must be public.

dtzSiFive opened this pull request 11 months ago

[Emit] Use FileOp to emit metadata

nandor opened this pull request 11 months ago

[ImportVerilog] Rename `Context` to `Converter`

fabianschuiki opened this issue 11 months ago

[Emit] Emit SV ops nested in a file

nandor opened this pull request 11 months ago

[ImportVerilog] Convert empty modules and instances

fabianschuiki opened this pull request 11 months ago

[FIRRTL] Infer Widths Unbreakable Loop Checking Performance Issues

seldridge opened this issue 11 months ago

[FIRRTL] Put layer collateral in testbench dir

seldridge opened this pull request 11 months ago

[Ibis] Split ContainerOp in two

teqdruid opened this pull request 11 months ago

[FIRRTL] Reject ref statements in 4.0.0+.

dtzSiFive opened this pull request 11 months ago

[CreateSiFiveMetadata] Generate firrtl.class instead of om.class

prithayan opened this pull request 11 months ago

[HGLDD] Don't access instance ports as hierarchical path

fabianschuiki opened this issue 11 months ago

[FIRRTL][LowerLayers] Clean up names of artifacts generated by layers

rwy7 opened this pull request 11 months ago

[firtool] Allow specialization of layers

seldridge opened this issue 11 months ago

[FIRRTL][CAPI] Add function for importing annotations

SpriteOvO opened this pull request 11 months ago

[Emit] Emit black boxes through `emit` ops

nandor opened this pull request 11 months ago

[FIRRTL] Add folders for IntegerMulOp

mikeurbach opened this issue 11 months ago

[ESI] Ditch Capnp and replace it with Protobuf/gRPC

teqdruid opened this issue 11 months ago

[FIRRTL] Dedup memory wrapper modules in LowerMemory

tymcauley opened this pull request 11 months ago

[FIRRTL] Generate Layer Collateral For All Public Modules

seldridge opened this issue 11 months ago

[LTL] Add fundamental operators

liuyic00 opened this pull request 11 months ago

[LowerFirReg] Reimplement the mux reachability analysis

prithayan opened this pull request 11 months ago

[FIRRTL] Add folders for IntegerAddOp

mikeurbach opened this issue 11 months ago

[arcilator] Introduce simulation orchestration subdialect

Moxinilian opened this pull request 11 months ago

CFToHandshake header depends on Transforms but doesn't actually ensure the dependency is built

mikeurbach opened this issue 11 months ago

integration_test: Add FIRRTL ref/public/agg ABI test.

dtzSiFive opened this pull request 11 months ago

LLVM bump

darthscsi opened this pull request 11 months ago

Ibis.class must implement symboltable if ibis.container is to be nested below

darthscsi opened this issue 11 months ago

Add test_en port to EICG in extract instances unit tests

mwachs5 opened this pull request 11 months ago

[firtool] Add option to disable black box resource

unlsycn opened this pull request 11 months ago

[LTL to Core] Add support for overlapping and non-overlapping implications without SVA

dobios opened this pull request 11 months ago

[ImportVerilog] Update to Slang 4

fabianschuiki opened this pull request 11 months ago

[HW] Make HWInstanceLike agnostic of the number of targets

nandor opened this pull request 11 months ago

[HW] Remove the cache-based lookup method from HWInstanceLike

nandor opened this pull request 11 months ago

[LinkModules] Add support to link hw modules

prithayan opened this pull request 11 months ago

[LTL] Add operators to enhance expressive power

liuyic00 opened this issue 11 months ago

[FIRRTL] CheckCombCycles ignores foriegn ops.

darthscsi opened this pull request 12 months ago

[FIRRTL] Dedup should update class reference ports if classes dedup.

mikeurbach opened this issue 12 months ago

[FIRRTL] Standalone initialization checking pass

darthscsi opened this pull request 12 months ago

Will the `AttributeAnnotation` support setting the target to port?

Discreater opened this issue 12 months ago

[NFC] try cleaner fix to windows issue

darthscsi opened this pull request 12 months ago

[FIRRTL] XFAIL'ing the mem-taps tests on Windows

teqdruid opened this pull request 12 months ago

Bump LLVM

darthscsi opened this pull request 12 months ago

[FIRRTL] Chisel assertions are translated into concurrent SVA rather than immediate SVA

techninja1008 opened this issue about 1 year ago

[FIRTOOL] Fallback to outDir for empty chiselInterfaceOutDir

poemonsense opened this pull request about 1 year ago

[NFC] Convert getPortAttributes back to ArrayRef

darthscsi opened this pull request about 1 year ago

[FIRRTL] Framework for intrinsic lowering

nandor opened this pull request about 1 year ago

[Scheduling] Rethink use of macros in problem classes

jopperm opened this issue about 1 year ago

[firrtl] Improve LayerSink with scc_iterator

seldridge opened this pull request about 1 year ago

[firrtl] Add Connection Graph

seldridge opened this pull request about 1 year ago

[circt-mc] Introduce `circt-mc` (supersedes #4647)

TaoBi22 opened this pull request about 1 year ago

[InstancePath] Add accessors to allow ops to reference multiple targets

nandor opened this pull request about 1 year ago

[Dedup][FIRRTL] SRAM modules not deduped when using memory macro replacement

tymcauley opened this issue about 1 year ago

Add lowering for ILA Probe Intrinsic

adkian-sifive opened this pull request about 1 year ago

[Arc] Improve how memory writes are legalized

maerhart opened this issue about 1 year ago

[FIRRTL][LowerTypes] Keep the order of bundle fields in lowered `cat`

SpriteOvO opened this pull request about 1 year ago

[Ibis] Refactor to use inner symbols

mortbopet opened this pull request about 1 year ago

[LLHD] Typed pointers are deprecated (warning)

dtzSiFive opened this issue about 1 year ago

[ExportVerilog] Unpacked array assignment to wire

teqdruid opened this issue about 1 year ago

[FIRRTL] Bitcasts reverse bundle field order in LowerTypes

fabianschuiki opened this issue about 1 year ago

LLVM pointers without inner type cause stores to disappear in LLHD lowering

fabianschuiki opened this issue about 1 year ago

[Arc] Split large LLVM functions

fabianschuiki opened this issue about 1 year ago

[MSFT] Add module-level PD capability

mortbopet opened this pull request about 1 year ago

[PipelineToHW] Add optional power-on values to control registers

mortbopet opened this pull request about 1 year ago

[Seq] Remove custom printer/parser for `seq.compreg(.ce)` ops

mortbopet opened this pull request about 1 year ago

[FIRRTL] Disallow rwprobe/forceable of non-passive.

dtzSiFive opened this pull request over 1 year ago

[MSFT] Add multicycle path op

mortbopet opened this pull request over 1 year ago