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github.com/llvm/circt

Circuit IR Compilers and Tools
https://github.com/llvm/circt

Chisel design with inline blackbox verilog generates `.sv` output with filenames at the end

carlosedp opened this issue almost 2 years ago

PrettyPrinter: init, w/convenience classes.

dtzSiFive opened this pull request almost 2 years ago

[Seq] Add `seq.fifo` ODS and rationale

mortbopet opened this pull request almost 2 years ago

[FIRRTL] Add Aggregate creation ops and aggregate constants

darthscsi opened this pull request almost 2 years ago

[StdToHandshake] Error on unshaped unidimensional arrays

mortbopet opened this pull request almost 2 years ago

[SV] SV to llvm conversions support

cepheus69 opened this issue almost 2 years ago

PrettyPrinterBuilder.h: init PPBuilder, PPBuilderStringSaver, PPStream

dtzSiFive opened this pull request about 2 years ago

[NFC] Cache sybmol lookup removing O(N^2) behavior from CircuitOp::verify

darthscsi opened this pull request about 2 years ago

[FIRRTL] Implement out-of-bounds as array extension

darthscsi opened this pull request about 2 years ago

Don't read lowering options from hidden global options

darthscsi opened this pull request about 2 years ago

Convert binary muxes to ifs when feeding seq.firreg

darthscsi opened this pull request about 2 years ago

[FIRTOOL] Run canonicalization prior to seq lowering.

darthscsi opened this pull request about 2 years ago

[Comb] Add a folder for simple binary values

darthscsi opened this pull request about 2 years ago

[NFC] LLVM bump for 2022/09/14

darthscsi opened this pull request about 2 years ago

[FIRRTL][WireDFT] use enable signal to name added ports.

dtzSiFive opened this pull request about 2 years ago

[FIRRTL] Improved code generation for register initialization

darthscsi opened this pull request about 2 years ago

[COMB] Add flag to assert binary behavior.

darthscsi opened this pull request about 2 years ago

[FIRRTL] Support optional version in fir files

darthscsi opened this pull request about 2 years ago

Convert firrtl IsX assert forms to real ops

darthscsi opened this pull request about 2 years ago

[LLHDToLLVM] Signals declared in llhd.proc are never initialized thus leading to simulator crash

maerhart opened this issue about 2 years ago

Bump LLVM to dd74d3117de0fd96383beeb4b4b913efcb9f4328

darthscsi opened this pull request over 2 years ago

Treat regreset the same in its initial lattice value as reg

darthscsi opened this pull request over 2 years ago

[FIRRTL] Remove old canonicalization patterns and fix NodeBypass

darthscsi opened this pull request over 2 years ago

[FIRRTL] Don't apply node bypass to node with droppable names

uenoku opened this pull request over 2 years ago

Add an op to constrain output statements in graph regions

darthscsi opened this pull request over 2 years ago

[FIRRTL] Document baseline naming and what symbols imply

darthscsi opened this pull request over 2 years ago

[Rational] Document inner symbol and references

darthscsi opened this pull request over 2 years ago

[NFC] Define InnerSymbol OpInterface and document rational in op

darthscsi opened this pull request over 2 years ago

Fewer Assigns of Constants in ExportVerilog

darthscsi opened this pull request over 2 years ago

Handle 0-length vectors in inferreset without connects to invalid

darthscsi opened this pull request over 2 years ago

Preserves FIRRTL names

darthscsi opened this pull request over 2 years ago

[comb] Missing Optimization to Build Reduction Ops

seldridge opened this issue over 2 years ago

Cmdline flags to deal with subcircuit

darthscsi opened this pull request over 2 years ago

[NFC] Change Canonicalization pattern to avoid exponential behavior

darthscsi opened this pull request over 2 years ago

Improve SV Case handling

darthscsi opened this pull request over 2 years ago

[ExportVerilog] Make module portlist one name per line, more like humans often do.

darthscsi opened this pull request over 2 years ago

[NFC] silence warning

darthscsi opened this pull request over 2 years ago

InferReset generates strict connects

darthscsi opened this pull request over 2 years ago

[FIRRTL] Don't lower types for invalid durring parsing.

darthscsi opened this pull request over 2 years ago

Add NLATable analysis and use it in PrefixModules

darthscsi opened this pull request over 2 years ago

[NFC] bump build env

darthscsi opened this pull request over 2 years ago

[NFC] bump build prior to llvm bump

darthscsi opened this pull request over 2 years ago

[IMCP] Mark aggregates overdefined and process them.

darthscsi opened this pull request over 2 years ago

[FIRRTL] Strict Connect op and starting to canonicalize all connects to it

darthscsi opened this pull request over 2 years ago

[NFC,FIRRTL] Reorder worklist for IMConstProp

darthscsi opened this pull request over 2 years ago

[NFC] Bump llvm to b0cd3abf032e

darthscsi opened this pull request over 2 years ago

[NFC] Simplify name preservation in LowerTypes

darthscsi opened this pull request over 2 years ago

[HW] Preserve names on variadics during generation and export

darthscsi opened this pull request over 2 years ago

[FIRRTL][Dedup] Memories reusing NLAs on the op and a port only update 1 or the other

youngar opened this issue over 2 years ago

[FIRRTL] retain node names when sensible

darthscsi opened this pull request over 2 years ago

hw.probe for late binding to nameless values

darthscsi opened this pull request almost 3 years ago

[GrandCentralTaps] Connect port with fieldID

uenoku opened this pull request almost 3 years ago

[FIRRTL] handle testbench dir annotation in combination with dut annotation

darthscsi opened this pull request almost 3 years ago

[ExportVerilog] Emit modules in descending order of module size

uenoku opened this pull request almost 3 years ago

make firtool output options and pipeline structure a bit more sensible

darthscsi opened this pull request almost 3 years ago

[FIRRTL] Fix use-after-free of ops erased during assert parsing

fabianschuiki opened this pull request almost 3 years ago

[Simulator] UB when using llhd.shr on signal

maerhart opened this issue about 3 years ago

[Simulator] Crash when initializing `llhd.sig` with non-constant value

maerhart opened this issue about 3 years ago

[PyCDE] Create pipeline to create and publish python wheel

teqdruid opened this issue about 3 years ago

[LLHD] llhd-sim unable to simulate generated llhd dialect

LindYu opened this issue over 3 years ago

Support for inferring result types

GeorgeLyon opened this issue over 3 years ago

[LLHD] Add for-loop operation

maerhart opened this pull request about 4 years ago