github.com/llvm/circt issues | Ecosyste.ms: OpenCollective

[LTL] Add repeat and until operators

liuyic00 opened this pull request 8 months ago

[FIRRTL][LowerAnnotations] Reject non-local fullasyncreset anno's.

dtzSiFive opened this pull request 8 months ago

[FIRRTL][InferResets] Fix fullasyncreset diag to use right name.

dtzSiFive opened this pull request 8 months ago

[FIRRTL] docs: fullasync annotation targets signal not module.

dtzSiFive opened this pull request 8 months ago

[FIRRTL][Dedup] Alter dedup group handling, avoid exponential behavior.

dtzSiFive opened this pull request 8 months ago

[FIRRTL][SFCCompat] Fix tests and handling of fullasyncreset on non-port.

dtzSiFive opened this pull request 8 months ago

Elaborate chisel type annotation from firtool to generate debug information for the Tywaves project

rameloni opened this issue 8 months ago

[Verif] Introduce a clocked assertion `verif.clocked_assert`

dobios opened this issue 8 months ago

[FIRRTL] Drop dead ScalaClassAnnotation.

dtzSiFive opened this pull request 8 months ago

[FIRRTL] Add inline convention to layers

seldridge opened this pull request 8 months ago

[FIRRTL] Performance Degradation in Dedup Runtime between Chisel3.6 and Chisel6

Heaton15 opened this issue 8 months ago

[Seq] Fix compreg printer printing two spaces

Moxinilian opened this pull request 8 months ago

[SV][ExportVerilog] Add sv.func, sv.func.call{.procedural}, sv.func.dpi.import

uenoku opened this pull request 8 months ago

[SMT] Added support for :pattern attribute

luisacicolini opened this pull request 8 months ago

[firtool] Integrate AssertProperty lowering into BTOR2 pipeline

dobios opened this pull request 8 months ago

[LTL to Core] Add lowering for AssertProperty operations

dobios opened this pull request 8 months ago

[SMT] Add quantifier support to LLVM lowering

maerhart opened this pull request 8 months ago

[Arc] Hoist reset value in CompReg when lowering for simulation

Moxinilian opened this pull request 8 months ago

[FIRRTL] Output directory control for layers and modules

rwy7 opened this pull request 8 months ago

Printf-encoded verification deprecation

dtzSiFive opened this issue 8 months ago

[ESI][runtime] Make cmake-distributed header include-able

mortbopet opened this issue 8 months ago

[PyCDE,Ibis] Crash on no-argument method wrapping

mortbopet opened this issue 8 months ago

[HW] Inner symbols dropped by InlineModules

uenoku opened this issue 8 months ago

[ExportVerilog] Ensure DivS/ModS are signed regardless of context.

dtzSiFive opened this pull request 8 months ago

[HW to BTOR2] Add support for encoded assertions

dobios opened this pull request 8 months ago

[HW] Moved and renamed arc/inlineModules to hw/flattenModules

dobios opened this pull request 8 months ago

[NFC] LLVM Bump

darthscsi opened this pull request 8 months ago

[NFCI] Document division and the rational for the handling of divide by zero

darthscsi opened this pull request 8 months ago

[FIRRTL][ExportVerilog] Signed Division Bug

seldridge opened this issue 8 months ago

Fix invalid rewriter API usages

7FM opened this pull request 8 months ago

[Comb] Officialize support for zero-width integers

Moxinilian opened this pull request 8 months ago

[LLHD] Replace entity with module

maerhart opened this pull request 8 months ago

[FIRRTL] Canoncializations of not( cmp )

darthscsi opened this pull request 9 months ago

[HWToLLVM][Arc] Add out-of-bounds handler for array accesses

fzi-hielscher opened this pull request 9 months ago

[FIRRTL] Don't fail compilation when Dedup group annotation is on EICG_wrapper

uenoku opened this pull request 9 months ago

[Python][HW] hw.WireOp inner_sym is inconvenient to use

nickelpro opened this issue 9 months ago

SCF To Calyx Support Float Add and Float SeqMemory Read/Write

jiahanxie353 opened this pull request 9 months ago

Pipeline For Lowering PyTorch Tensor Add To FPGA

jiahanxie353 opened this pull request 9 months ago

[Scheduling] computeStartTimesInCycle: clear before recomputation

7FM opened this pull request 9 months ago

[ImportVerilog] Add conditional operator.

angelzzzzz opened this pull request 9 months ago

[HWToLLVM] ArrayGet lowering produces out-of-bounds memory access

fabianschuiki opened this issue 9 months ago

[Arcilator] Integration tests failures without check-circt

teqdruid opened this issue 9 months ago

[firtool] btor2 integration

dobios opened this pull request 9 months ago

[ESI] Add cmake switch to enable ESI_COSIM

mortbopet opened this pull request 9 months ago

[CombToArith] Fix coarsening of division by zero UB

maerhart opened this pull request 9 months ago

[FIRRTL][CAPI] Add function for getting mask type

SpriteOvO opened this pull request 9 months ago

[DC] Add merge lowering

mortbopet opened this pull request 9 months ago

[HandshakeToDC] Fix constant unit-rate op lowering

mortbopet opened this pull request 9 months ago

[HandshakeToDC] Add pack/unpack lowering patterns

mortbopet opened this pull request 9 months ago

[MooreToCore] Lower moore operators into comb or hw.

hailongSun2000 opened this pull request 9 months ago

[FIRRTL][LowerTypes]Node cannot be declared with a flip field?

wky17 opened this issue 9 months ago

[Arc] Generates signalling code

hovind opened this issue 9 months ago

[FIRRTL] Disambiguate paths when possible in ResolvePaths.

mikeurbach opened this pull request 9 months ago

[FIRRTL] Error if asked to add a port to a public module.

dtzSiFive opened this pull request 9 months ago

[FIRRTL,PASS] Simple module summary looking for likely to dedup larger or numerous modules. This is to guide developers in using chisel better.

darthscsi opened this pull request 9 months ago

[Handshake] Add merge decomposition pattern

mortbopet opened this pull request 9 months ago

[HW] Rework InnerSym infra to support nested symbol tables

mortbopet opened this pull request 9 months ago

Bump llvm

azidar opened this pull request 9 months ago

[comb] Break out some canonicalizations into optimization pass

teqdruid opened this issue 9 months ago

Duplicate expressions possibly due to spilled event control expressions in LTL statements

jackkoenig opened this issue 9 months ago

[ImportVerilog] Add case statement.

angelzzzzz opened this pull request 9 months ago

[Arc] Fix segfault in SplitLoops

Moxinilian opened this pull request 9 months ago

[FIRRTL] sizeof intrinsic doesn't work on bundles

dtzSiFive opened this issue 9 months ago

[FIRRTL] isX lowering doesn't work for bundles

dtzSiFive opened this issue 9 months ago

Looking for circt==1.48.1.dev34

rkshthrmsh opened this issue 9 months ago

[FIRRTL][InferWidths] When there is no unique minimal solution for width constraints, what should be the width?

wky17 opened this issue 9 months ago

[FIRRTL] Gather intrinsic lowering via dialect interface.

dtzSiFive opened this pull request 9 months ago

[FIRRTL] ‘firtool’ crashes with an error when receives a ‘fir’ file with no main module

iagrigorov opened this issue 9 months ago

[FIRRTL] Make input probes illegal

dtzSiFive opened this pull request 9 months ago

[SMT] Added weight attribute support for ExportSMTLIB

luisacicolini opened this pull request 9 months ago

[FIRRTL] Not generate "automatic logic" in the output SystemVerilog file

SinaKarvandi opened this issue 9 months ago

[HWToBTOR2] Deduce resets from (Fir)RegOps

TaoBi22 opened this pull request 9 months ago

[FIRRTL] no back-prop for width of mux selectors, support narrower

dtzSiFive opened this pull request 9 months ago

[FIRRTL] Add debug logging to dedup

jackkoenig opened this pull request 9 months ago

llvm: bump

dtzSiFive opened this pull request 9 months ago

[SMT] Add quantifier attribute and pattern support to ExportSMTLIB

maerhart opened this issue 9 months ago

Update annotation handling to fix partial field reset behavior

adkian-sifive opened this pull request 9 months ago

[FIRRTL][LowerIntrinsics] Add stat and preserve if no changes.

dtzSiFive opened this pull request 9 months ago

[Ibis] Divorce port name (hints) from port symbol names

mortbopet opened this pull request 9 months ago

[circt-lec] Port to SMT dialect based compiler pipeline

maerhart opened this pull request 9 months ago

[ImportVerilog] Fix the types mismatch for variable declarations.

hailongSun2000 opened this pull request 9 months ago

[ImportVerilog] Add replicate and extract operations.

hailongSun2000 opened this pull request 9 months ago

[SMTToLLVM] Add support for most expressions

maerhart opened this pull request 9 months ago

[FIRRTL] Use lower-sigs to handle port scalarization of internal modules. This removes Lower Types from dealing with it in anticipation of Lower Types being simplified.

darthscsi opened this pull request 9 months ago

[Comb] Remove more idempotent operands

hovind opened this pull request 9 months ago

[SMT] Add lowering to LLVM IR

maerhart opened this pull request 9 months ago

[FIRRTL] Use a flag to implement scalarization of internal modules. …

darthscsi opened this pull request 9 months ago

[SMT] Minor width related fixes for BitVectorAttr

fzi-hielscher opened this pull request 9 months ago

[FIRRTL] Drop support for long-unused subcircuit annotations.

dtzSiFive opened this pull request 9 months ago

[FIRRTL][NFC] Remove dead signal driving annos.

dtzSiFive opened this pull request 9 months ago

[FIRRTL] Generic intrinsic parsing/emitter support

dtzSiFive opened this pull request 9 months ago

[FIRRTL] Fixup visit ops miscategorized.

dtzSiFive opened this pull request 9 months ago

[Ibis] fix invalid `std::optional` dereferencing

mortbopet opened this pull request 9 months ago

Bump LLVM to latest

seldridge opened this pull request 9 months ago

[FIRRTL][CAPI] Allow constructing integers larger than 64 bits

SpriteOvO opened this pull request 9 months ago

[NFC] Cache common lookups in ModuleType

darthscsi opened this pull request 9 months ago

[FIRRTL] Split intrinsic op into expr vs stmt.

dtzSiFive opened this pull request 9 months ago

[FIRRTL] Expose clock dividers as a FIRRTL intrinsic

nandor opened this pull request 9 months ago

[CFToHandshake] Move `Transforms` dependency to implementation

mortbopet opened this pull request 9 months ago

[Pipeline] Remove `Pure` trait from Pipeline operations

mortbopet opened this pull request 9 months ago