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github.com/llvm/circt

Circuit IR Compilers and Tools
https://github.com/llvm/circt

Calyx Binary Floating Point AddF Operator

jiahanxie353 opened this pull request 8 months ago
[Moore] Move array types into ODS

fabianschuiki opened this pull request 8 months ago
[Arc] Modify VectorizeOp to support AnyType

elhewaty opened this pull request 8 months ago
Calyx ConstantOp Support

jiahanxie353 opened this pull request 8 months ago
[Seq] Fix incorrect folder

uenoku opened this pull request 8 months ago
[ImportVerilog][Moore] Support union type

mingzheTerapines opened this pull request 8 months ago
[ImportVerilog] Support parameter constants.

angelzzzzz opened this pull request 8 months ago
[Moore] Introduce Mem2Reg to eliminate local variables

hailongSun2000 opened this pull request 8 months ago
[firtool] Add an option to export SV without SVA

dobios opened this pull request 8 months ago
[CI] Update github actions to use node.js 20

youngar opened this issue 8 months ago
LLVM bump

youngar opened this pull request 8 months ago
[OM] Rework Class and Object op to finish the move away from fields being symbols

mikeurbach opened this issue 8 months ago
[FIRRTL] Preserve all analysis if nothing happens

uenoku opened this pull request 8 months ago
[FIRRTL] Remove unused and expensive API, NFC

uenoku opened this pull request 8 months ago
[MooreToCore] Lower moore.variable into hw.wire.

hailongSun2000 opened this pull request 8 months ago
[FIRRTL] Limited invalid propagation.

darthscsi opened this pull request 8 months ago
[FIRRTL] Enable Wire Elimination

darthscsi opened this pull request 8 months ago
[LowerClasses] Ensure classes are instantiated by an object.

prithayan opened this pull request 8 months ago
[Arc] Allow VectorizeOp body to have multiple results

fabianschuiki opened this issue 8 months ago
[Arc] Allow uniform operands to the VectorizeOp

fabianschuiki opened this issue 8 months ago
[FIRRTL] Register reset elimination based on invalid can look through nodes.

darthscsi opened this pull request 8 months ago
[Support] Print timestamp for logging

uenoku opened this pull request 8 months ago
[FIRRTL] Convert Wires into Nodes

darthscsi opened this pull request 8 months ago
[ImportVerilog] Support set membership operator.

angelzzzzz opened this pull request 8 months ago
[LTL] Add ops that allow for most of SVA to be modeled with LTL

dobios opened this pull request 8 months ago
[FIRRTL] Don't put names on constants

darthscsi opened this issue 8 months ago
Duplicate hw.hierpath being created

darthscsi opened this issue 8 months ago
[PyCDE] Move build and publishing pipeline into repo

teqdruid opened this pull request 8 months ago
[Arc] Initial SLP support

elhewaty opened this pull request 8 months ago
[FIRRTL][LowerClasses] Improve performance, NFC

uenoku opened this pull request 8 months ago
[ESI][Runtime] Refactor cosim backend to be thread safe

teqdruid opened this pull request 8 months ago
Add script to run filecheck_lint, add to CI

dtzSiFive opened this pull request 8 months ago
FileCheck directive fixup, now filecheck_lint-clean.

dtzSiFive opened this pull request 8 months ago
[FIRRTL] Fix width of attribute in MuxPadSel canonicalizations.

dtzSiFive opened this pull request 8 months ago
[LLHD] Fix operand assignments not going through rewriter.

dtzSiFive opened this pull request 8 months ago
[Comb] Fix MuxRewriter to eraseOperand in rewriter-aware way.

dtzSiFive opened this pull request 8 months ago
[HW] Fix pattern returning success() without changing.

dtzSiFive opened this pull request 8 months ago
[Handshake] Fix canonicalizer not going through rewriter for RAUW.

dtzSiFive opened this pull request 8 months ago
[Calyx] Verified-valid IR crashes in canonicalizer

dtzSiFive opened this issue 8 months ago
[Caylx] canonicalization results in invalid IR: ifOp w/empty else

dtzSiFive opened this issue 8 months ago
[FIRRTL][Folds] Fix patterns to use rewriter for RAUW

dtzSiFive opened this pull request 8 months ago
[SV][Folds] Fix ForOp canonicalizer to use rewriter.

dtzSiFive opened this pull request 8 months ago
`-DMLIR_ENABLE_EXPENSIVE_PATTERN_API_CHECKS=ON` might have found some invalid API usages

7FM opened this issue 8 months ago
[CreateSifiveMetadata] Fix a typo in the field name

prithayan opened this pull request 8 months ago
[ESI][Cosim][NFC] Refactor cosim to divorce capnp from DPI

teqdruid opened this pull request 8 months ago
[LTL] Add clocked and disabled property types

dobios opened this pull request 8 months ago
[FIRRTL][Intrinsics] source materialization for inferred types.

dtzSiFive opened this pull request 8 months ago
[Sim] Add DPI func/call and lowering

uenoku opened this pull request 8 months ago
[FIRRTL][NFC] Replace intmodules with intrinsic expressions in test.

dtzSiFive opened this pull request 8 months ago
[HW] hw.module.extern does not print non-identifier names correctly

Moxinilian opened this issue 8 months ago
[ImportVerilog] Support member-access expression

mingzheTerapines opened this pull request 8 months ago
Support member-access expression.

mingzheTerapines opened this pull request 8 months ago
[HW][LTL][SV] Unify EventControl

maerhart opened this pull request 8 months ago
[Moore] Simplify and move RealType definition into ODS

fabianschuiki opened this pull request 8 months ago
[Moore] Move IntType definition into ODS

fabianschuiki opened this pull request 8 months ago
Factor out ClockEdgeAttr definitions

fabianschuiki opened this issue 8 months ago
[ESI][Runtime] Don't pull down JSON dependency if already defined

teqdruid opened this pull request 8 months ago
[ESI][Runtime] Remove C++ includes from wheels

teqdruid opened this pull request 8 months ago
[FIRRTL][LowerXMR] Simplify now that input probes aren't supported

dtzSiFive opened this issue 8 months ago
[FIRRTL][Import] Remove support for printf-encoded verif.

dtzSiFive opened this pull request 8 months ago
[ESI][Runtime] Revert to C++17

teqdruid opened this pull request 8 months ago
cmake: circt install directory for CAPI

dtzSiFive opened this pull request 8 months ago
[Arc] Add SplitFuncsPass

TaoBi22 opened this pull request 8 months ago
[OM] Separates OM object fields verifier to a dedicated pass

uenoku opened this pull request 8 months ago
[CombToSMT] Make result of div-by-zero undefined

maerhart opened this pull request 8 months ago
[SV] Add `sv.reserve_names` op to disallow names

teqdruid opened this pull request 8 months ago
[HW] HWModule (et. al.) should have separate symbol and name to be emitted

teqdruid opened this issue 8 months ago
[Verif] Add clocked Assert Assume Cover ops

dobios opened this pull request 8 months ago
[FIRRTL] Add condition expansion for ExpandWhens on Property intrinsics

dobios opened this pull request 8 months ago
[OM] Add IsolatedFromAbove to OMClass

uenoku opened this pull request 8 months ago
[Moore] Improve declaration and instantiation of SVModule operation

cepheus69 opened this pull request 8 months ago
[docs] Add cmake flags that reduce memory usage

dobios opened this pull request 8 months ago
[CAPI] Add circt-capi target and build it in CI

fabianschuiki opened this pull request 8 months ago
[FIRRTL] Don't prefix an empty label for unclocked assume.

dtzSiFive opened this pull request 8 months ago
[ExportVerilog] Support sv.func.* op emission

uenoku opened this pull request 8 months ago
[AddSeqMemPorts] Add hierpathop to verbatim, instead of raw instance path

prithayan opened this pull request 8 months ago
[HW][LegalizeModules] Avoid segmentation fault

hovind opened this pull request 8 months ago
[docs] Add basic pass tutorial

dobios opened this pull request 8 months ago
[Moore] Make simple bit vectors a proper MLIR type

fabianschuiki opened this pull request 8 months ago
[FIRRTL] Remove support for printf-encoded verification, tests.

dtzSiFive opened this pull request 8 months ago
[FIRRTL] Reject intrinsic modules >= 4.0.0

dtzSiFive opened this pull request 8 months ago
[FIRRTL][NFC] Drop use of intmodule's in tests.

dtzSiFive opened this pull request 8 months ago
(For LLVM Bump testing)[FIRRTL] AnnoTarget: use LLVM style casts

dobios opened this pull request 8 months ago
[HWToSMT][circt-lec] Resolve transitive !smt.bool -> i1 -> !smt.bv<1> casts.

fzi-hielscher opened this pull request 8 months ago
[SV] Add DPI import op

uenoku opened this pull request 8 months ago
[ExportVerilog][HW] Introduce HWEmittableModuleLike interface and use it for Prepare, NFC

uenoku opened this pull request 8 months ago
[SV] Add sv.func, sv.return and sv.func.call operations

uenoku opened this pull request 8 months ago
[FIRRTL] AnnoTarget: use LLVM style casts

youngar opened this pull request 8 months ago
[ESI][Runtime] Python wheel now provides cpp support

teqdruid opened this pull request 8 months ago
[pycde] Disallow structs with zero fields

teqdruid opened this pull request 8 months ago
[firtool] Add FlattenModulesPass to the btor2 emission pipeline

dobios opened this pull request 8 months ago
[NFC][clang-tidy] Disallow global 'using' directives in headers

fzi-hielscher opened this pull request 8 months ago
[ARC][CAPI] Add basic C API for initializing ARC

devins2518 opened this pull request 8 months ago
[HW][FlattenIO] Flatten io arrays

hovind opened this pull request 8 months ago
[ImportVerilog] Fix unknown name caused by local variables.

hailongSun2000 opened this pull request 8 months ago
[CAPI][Moore] Remove deprecated types

hovind opened this pull request 8 months ago
LLVM Bump

dobios opened this pull request 8 months ago
[Pipeline] Verify >0 result types for LatencyOp

mortbopet opened this pull request 8 months ago
[FSM]New builders for StateOp and TransitionOp.

HahaLan97 opened this pull request 8 months ago
[Moore] A new pass to delete local temporary variables.

hailongSun2000 opened this pull request 8 months ago