Adds a new operation to the MSFT dialect which specifies a multicycle path constraint in between...

Mustn't insert things after the terminator!

This is safe since it's just an enum from a header. Better since it
avoids duplication.

Treat blockargs like other values and let the asm name hint interface compute names for them. If...

RecursiveMemoryEffects and RecursivelySpeculatable traits provides automatic derivation of side-...

seq.compreg asm syntax change

* add emission for Calyx std_signext

* fix tests

Update ETC to add non-empty and unique port names.

---------

Co-authored-by: Nandor Licker...

firrtl.instance with lowerToBind is lowered into bound instance and symbols are created for the ...

This commit adds strip option to drop name pass. Even though there is none option but none optio...

Previously Namespace::newName could return empty string for empty string.
This is a problematic...

This PR does an overhaul of how path related operations work in the OM dialect.

When OM class...

This fixes a windows build failure

The default `install` command doesn't install LLVM utils Filecheck/not/count. Downstream users o...

This commit adds pupport for MLIR plugins for circt-opt

Instead of the `--instantiate-companion-only` flag, Grand Central now takes a `--companion-mode`...

Add the debug locations to the evaluator value, which will be used to generate info fields
of ...

Resulting generated .sv:
```mlir
hw.module @testPowerOn(in %arg0: i32, in %arg1: i32, in %go: ...

Removed in favor of using a generated parser + a couple of custom directives to resolve the opti...

This PR ads MLIR pass plugin functionality to firtool pipeline to dynamically load pass plugins ...

In doing so, also opt to move to a keyword style assembly format, rather than a flat list of ope...

Keep FIRRTL-only for now due to dependence on dialect-specific
mechanism to get port number fro...

Previously: #5780.

Fixes #6259.

(along with #5835 for the specific FIRRTL input)

Keep forceable for now-- it's needed for uninferred resets presently,
and has slightly better (...

These disappear early but some diagnostics, such as flow checking,
use this method so implement ...

Having an `sv.xmr.ref` op inside a procedural block such as
`sv.alwayscomb` triggers an asserti...

This commit adds support for graph regions for evaluator.

`ReferenceValue`, a new subclass of...

This adds more path types which will be used for greater safety in OMIR. This
change splits reg...

Mostly broken due to hw.module asm format change. Also, the cocotb tests
have been broken for s...

CIRCT will eventually want to be able to emit debugging information
alongside its Verilog and o...

The current logic doesn't support freezing paths with multiple public
modules. In the current s...

Lower `arc.model` operations to an eval function similar to what
Verilator creates. Instead of ...

1. During prepare scheduling, we also assign `ssp.operator_type` attributes to the operations. T...

Remove canonicalizations of RegOp related to invalid values since
interpretation is context-dep...

The following mux canonicalizations have been added:
- mux(eq(a, b), a, b) -> b
- mux(neq(a, b...

Extract the Arc-to-Func lowering from the LLVM lowering pass and make it
a separate step in the...

While lowering an ExtModule, if it has a defname set, use that for the
lowered ExtClass name. T...

We expect to run this tool on post-export IR, so load the appropriate dialects in the context.

Looks like this test really does require Questa.

Wasn't getting caught by Github CI since this required questa. Changed
to any IEEE simulator and...

`ibistool` was missing in the tool list in the integration test making it crash, so I simply add...

This pass constructs a `pipeline.scheduled` which uses `seq.clock_type`..

Needed by the `ibis.pipeline_header` parser

This PR adds extra IMCP just after register optimization pass.
We separated register optimizati...

Previously, any `PortInfo` attribute dictionary provided in `ModulePortInfo` would be disregarde...

Dataflow methods can be converted to containers - which allows us to leverage all of the existin...

Lower away bundle types into channels. Doesn't support reset signals since the [un]pack ops don'...

This consults the register's fanout, and only pulls muxes into if/else
structure if they are on...

The default-initialized std::atomic doesn't actually contain a valid
bool, it contains a value s...

We currently blindly align the types and names of declarations, which
causes excessively large ...

Add and enable support for input probes.

Per spec, all uses (XMR read/force/release) of a pro...

Move lower to hw to preserve port order instead of doing inputs then outputs.

This commit implements PathAttr CAPI and Python bindings.

Factors out the conversion s.t. it can be run on arbitrary operations. To facilitate this, the c...

Post-argification it makes a lot of sense to have an IsolatedFromAbove block:
1. for pass sched...

Prevent the creation of HW struct/union types containing multiple fields of the same name to avo...

Closes #6223

* add calyx.undef

* rename op to `undefined` since `undef` doesnt work

* Move simple defin...

...which still won't get shown given an upstream bug.

They were added in 3.2.0.