This simplifies the `arc.state` operation by always requiring latency > 0 and uses `arc.call` op...

Change a test to be called "layers.fir" and not "groups.fir". Change it
internally to use layer...

This change seems to make the test problem go away.

In Python3.8, must use `typing.Dict` to subscript types.

Worked until now, but the upcoming llvm bump doesn't like it.

We are running out of space in PyPI, so this removes support for
versions Python 3.9 and Python ...

Signed-off-by: Schuyler Eldridge <[email protected]>

Dummy internal paths must be added to expanded ports.

We intended to keep the InstanceGraph up to date, but when we
completely erase FIRRTL ClassOps,...

Add a utility in FIRRTLOps.cpp for getting an optional attribute from an
array of named attribut...

Signed-off-by: Schuyler Eldridge <[email protected]>

Fix an issue in the `LowerSignatures` pass where instances would discard
their location and inh...

Match what we use in CI.

Give write permissions to jobs that upload release assets.
Set the release-tag explicitly so th...

Change boilerplate llvm::dbgs() printing to use a new utility. This
avoids duplication of the s...

Add two helpers for printing boilerplate that is commonly used when
generating LLVM debugging in...

Repair the ability to implement services in PyCDE. I broke this some
months ago and never got a...

Signed-off-by: Schuyler Eldridge <[email protected]>

Being explicit has benefits too, but simplify.

Adapting to new runtime API.

- Mirror the C++ design and type hierarchy.
- Add [de-]serialization support to/from Python obj...

And add a test as well.

- Moves classes around.
- Changes Type ownership.
- Cleans up #includes.
- Adds documentation

If a `HierPathOp` has a root module that is flattened and inlined, then donot
retop the root m...

We added a type replacer and used it to update the type of list create
ops previously, but a si...

Fixes #6533.

The logic that was moving the symbol from the port to the wire was
incorrectly assuming that a...

* Added missing tool in integration test

* Fixed formatting

* Fixed whitespace issue

* ...

Not to ToT, but to the parent of a problematic commit.

These will be tested with the emitter

Emit inline levels of hierarchy in the DI, introduced by the new
`dbg.scope` operation, as inli...

The `SpecializeOptions` pass eliminates instance choices and replaces them with instances target...

Modules generated by ETC are currently marked as public but it should be private. This change al...

This PR defines a ChainingCyclicProblem, which models a hybrid problem of ChainingProblem and Cy...

Allow `!arc.state` to carry HW structs and arrays. The state only has to
be able to compute the...

Enable the `InferStateProperties` pass in the arcilator pipeline and
make its enable and reset ...

A `comb.concat` operation with only a single operand would cause an
`arith.extui` to be emitted...

Add the `dbg.scope` operation to the debug dialect. The op creates an
additional level of hiera...

Make paths emitted into HGLDD companion files relative to the file
itself, or emit absolute pat...

This is a breaking change to chisel. Chisel outputs don't touch on aggregate ports, which this ...

The arc dialect currently provides its own `arc.clock_gate` operation.
Since the seq dialect ha...

- Rename Accelerator to what it really is: an AcceleratorConnection.
- Rename "Design" to "HWMo...

Add the `--fixup-eicg-wrapper` option to firtool and the LowerIntrinsics
pass. Setting the opti...

This PR has the following two changes:

* Fix module input and output port orders

* Add op...

https://llvm.org/docs/CodingStandards.html#don-t-use-default-labels-in-fully-covered-switches-ov...

* MLIR removed some uses of `const`, especially `.replaceAllUsesWith`
* In MLIR emitc, `call` w...

Parse explicitly for rwprobe case for better handling
and to avoid creating spurious indexing o...

This is the recommended way to manage access to PyPI from CD pipelines
moving forward. Our PyPI ...

Add rtl-sim to requires and %python before cosim runner.

Extend WireDFT to support wiring the test-enable signal to ClockGateIntrinsicOp's in same manner...

ArrayRef<BlockArgument> makes the elements 'const' unnecessarily,
causing issues with upcoming ...

Fixes a typo in the registration of conversion patterns of the
`HandshakeToHw` pass that would ...

The warning is too verbose and the header setup of CIRCT does not line up with it.