Minor change broke what was a brittle test. Broken by #4540.

Change the existing ReadMemOp to use an SSA Value for its destination
memory as opposed to a sym...

Signed-off-by: Schuyler Eldridge <[email protected]>

Fix a test that was erroneously failing for certain port source
locators.

Signed-off-by: Schuyl...

* Migrate to the new folding api

In the old folding API, folders would get an array of attrib...

The goal of this PR is to parse in FIRRTL debug source locations for module ports, and maintain ...

This PR reimplements #4451 revered by #4465. The bug was that `getOrCreateAggregateConstantAttri...

Instead of calling `_obj_to_value` from the support library, use some
OOP to leverage the `Type...

This moves the side-effecting call (`insertDependence`) out of an
assert. It still asserts the c...

Co-authored-by: Ram Sunder <[email protected]>

This fixes a problem where we do not respect the `isInOut` flag of the
PortInfo when adding bloc...

When we create the PortInfo object for a module, if the port is a
HW::InOutType, we strip it and...

When we added the flag to directly instantiate companions, we also
stopped generating interface...

Improve bad code:
- Cleanup imports.
- Complete the `Value` to `Signal` rename.
- Clarify arg...

Allows users to define structs as Python classes and use instances of that class in generators:
...

* explicit plumbing of values through the pipeline given gap between arrival time and use time

Add support for arithmetic and comparisons of IntSignals and python
integers by converting the i...

- Hide the CIRCT type behind `Type` -- most of the changes stem from this change.
- Uniquify Py...

This commit adds a version of the Calyx remove-groups pass tailored for
the FSM flow. Specifica...

This fixes a bug in `isExpressionEmittedInline` introduced by 1c38d707a3cc4e84631f7218a4a62e4501...

+ fix a stray printout.

The intention with this step is to
1. have a place to point people t...

Comitting an old piece of code I had lying around. The pass is modelled after the native calyx c...

Signed-off-by: Schuyler Eldridge <[email protected]>

Add "-lower-annotations-no-ref-type-ports" option to firtool. This is
an option that will cause...

Add a new pass option to the LowerAnnotations pass that will cause ref
type ports created by Wir...

Add an option that will cause Grand Central companion modules to not be
bound in (they are direc...

Add an option to the GrandCentral pass that will _not_ bind in the
companion module and will _no...

Signed-off-by: Schuyler Eldridge <[email protected]>

Fix a bug in the GrandCentral pass where weird types (IntegerType,
BooleanType, etc.) would, if ...

Fix a bug in the composition of the PrefixModules and ExtractInstances
passes. Because the latt...

* Bump LLVM submodule

Minimal progress, but worth sharing.

* compiling now

* clang-form...

Convert some inconsistent indentation in one FIRRTL test.

Signed-off-by: Schuyler Eldridge <sch...

Add private visibility to `systemc.cpp.func` in a few lit tests, which is
required for the up...

Nest the passes explicitly when adding to PassManager.
Required for the latest LLVM Bump, #4563...

Besides allowing some direct IR mutations, this also has proven to be
a non-obvious interaction ...

- Set a number of outputs from a generator via dicts.
- Get the outputs from an instance via a ...

Change the ExtractInstances pass to no longer include the final
extracted instance in the output...

Change the ExtractInstances pass to always create an ExtractSeqMems file
if the appropriate anno...

This PR fixes a race condition in LowerTypes with aggregate preservation mode. In the instance o...

Previously expressions feed into bound instances are anchored by wires
so that we can remotely g...

This PR removes ModuleNameManager from ExportVerilog. Previously it was necessary for ExportVeri...

Fix the InferResets pass to exit if any errors are discovered when
processing annotations. Prev...

Fix deficiency in the FIRRTL parser where the module location was always
overriding the port loc...

Support long-form version of option for readability.

Include usage in description to workarou...

Use the SSP dialect and `-ssp-schedule` instead.

Establish a nominal baseline for verilog generation.

Add a missing, but supported, annotation ExtractBlackBoxAnnotation to
the annotation records str...

Fixes #4569. For some reason VS2022 doesn't like the shorthand that was
being used here. This fi...

When enum attributes are generated, there's no option to restrict generation to
a particular di...

Refactor PyCDE module creation to a subclass based scheme. This is a breaking API change, but a ...

- Make WidthQualifiedTrait a type trait, renaming it to
WidthQualifiedTypeTrait.
- Rather th...

Convert all fieldID-related functions which are not already in the
FieldIDTypeInterface to use u...

Change the AddSeqMemPorts pass to mark ports created on the DUT (or the
top module) with DontTou...

Add test for error messages (which passes without this change).

Follow up to e1bd9e1.

Renaming the very generic `Value` class name to `Signal`. It's a bit of a stretch for things lik...

* SSA Maximization pass and utilities

This commit replaces liveness analysis within the Stand...

Helpful to repro and debug using circt-opt.

Teaches PyCDE how to play nice in the python global namespace. CIRCT is now "hidden" as `pycde.c...

Zero-length slices are perfectly valid, so don't assert on them.

Closes #3475. Also switch to relative imports in the hope that other projects (ie PyCDE) can inc...

Also, change the order of arguments for Bundle::get, so that context is first,
as generated by ...

A 'control register' is a single bit register which gets set and reset
based on pulses. Asserts...

Use a flag genStorageClass to let us continue to use a custom storage class.

The inline annotation location is invalid if none are specified,
and since the error isn't in i...

Can be used to provide nicer diagnostics or to help find supporting files like annotations.

Simple version bump to keep things up-to-date. The SCIP solver was recently re-licensed under Ap...

Signed-off-by: Schuyler Eldridge <[email protected]>

Remove all ability to parse the conditionally valid (validif) construct.
This construct was neve...

Signed-off-by: Schuyler Eldridge <[email protected]>

Introduce separate class hierarchies for signless integers (which PyCDE calls 'Bits') and signed...

... As well as adding aa missing argument to the PyCDE test which triggered this bug.

Fix a bug in CheckCombLoops pass, it was not handling paths between ground
type and aggregates...

Properly format the lit tests.

Switch to the new CheckCombLoops pass and add a flag
`--use-old-check-comb-cycles` to switch t...

Refactor the implementation to avoid redundant traversal.
This fixes a performance regression i...

Don't add values to the input set if they are the result of an op we
are already going to clone....

Statistics are useful, e.g. for metrics.

Insignificant impact on binary size (locally: +200K ...

For reset-less 1d array registers, replace an unitialized elemenent with
constant zero. For exa...

Bitcast is generally not allowed to be inlined but we can inline
if its user is (array)concat s...

HWMemSimImpl creates unpacked array registers for memory storage. However with aggregate preserv...