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github.com/llvm/circt

Circuit IR Compilers and Tools
https://github.com/llvm/circt

[ExportVerilog] More support for SV attributes (#4716)

Add SV attribiutes emission supports to module, instance,
case, always, always_comb, always_ff ...

e06c866b829670e60fa308282cd6f087faf52290 authored over 1 year ago by Hideto Ueno <[email protected]>
[PyCDE] Set dialect attributes on modules, expose flatten dialect attr (#4723)

Adds a 'Attribute' python attribute which can be used to set (CIRCT)
attributes on modules. Use...

45a793fd53b1bfdc03714c9b4a0537faa6ca55a6 authored over 1 year ago by John Demme <[email protected]>
[ESI] Option to flatten struct messages (#4712)

Some external modules (and modules which may instantiate our modules) expect multiple data ports...

65406409b025912b39e0614598200438c0e93490 authored over 1 year ago by John Demme <[email protected]>
[FIRRTLFolds] Add a mux canonicalize pattern (#4720)

Add the pattern mux(cond, 0, 1) -> ~cond
Fixes #4717

c4447004c344e5a3391a1d7546565197a7dd324f authored over 1 year ago by Prithayan Barua <[email protected]>
[Arc] Add arc conversion pass (#4697)

Add the `ConvertToArcs` conversion which collects the combinational
operations in a module body...

55e2230e3fd12d9ce43d825fe5242a2a3899e9c3 authored over 1 year ago by Fabian Schuiki <[email protected]>
[NFC][HW] Clang-tidy on the last commit

1027dfc11533dbd4313501152cb0e42913d2c92c authored over 1 year ago by John Demme <[email protected]>
[HW] Add builder for StructExplodeOp

StructExplodeOp only needs the info from the value which it's exploding.
Add a builder for that.

6b0d2df53ee7d10e748086938821ed1926f07951 authored over 1 year ago by John Demme <[email protected]>
[ESI] Add parameters to PureModule lowering (#4711)

Some low-level BSPs instantiate the top-level module with parameters. We
don't care about said ...

0928ce9dbb9ca41fa5046d95296a11da6e231f4e authored over 1 year ago by John Demme <[email protected]>
[CI] Add a workflow for building and uploading Python wheels. (#4710)

The workflow uses cibuildwheel to build the wheels, and uploads them
to GitHub. They're added t...

8d58e11f4f5a876e204a70a4b2c0ed1b29420022 authored over 1 year ago by Mike Urbach <[email protected]>
[PyCDE] Expose signaling and FIFO0 (#4705)

- Plumbing through signaling and adding it as an optional argument on Channel ports.
- Teach wr...

493e9f005576192c356b2893f711f491ae068de2 authored over 1 year ago by John Demme <[email protected]>
workaround for bram issue

c1f3e52f501b5d0f070bbcf5d0ceb055c57f73e2 authored over 1 year ago by Andrew Lenharth <[email protected]>
A bit more description

4fde94d2bf9c0d4c8a68e077536e72be40904016 authored over 1 year ago by Andrew Lenharth <[email protected]>
Another super annoying bug

80f23313e7cd6b1b0594fd2ebfc7632fd2b15268 authored over 1 year ago by Andrew Lenharth <[email protected]>
synthesis failure example documented

1d3743e4983e84b5420c52ee0e6b6ac77407d0df authored over 1 year ago by Andrew Lenharth <[email protected]>
[NFC] place for documenting interesting workarounds

28728872394727f03008b6618a61a0b5ee1fc242 authored over 1 year ago by Andrew Lenharth <[email protected]>
[NFC] Fixed insertInput/insertOutput

2916a6f12ed8b5f6aab3fd9847f507f6a5f4f85c authored over 1 year ago by Nandor Licker <[email protected]>
[LowerToHW] Use port locations for diagnostics, don't dump module. (#4708)

952de0ce82c3805927b36ef4b2a0a8303d9dbbb1 authored over 1 year ago by Will Dietz <[email protected]>
Unshallow CIRCT clone in uploadBinaries workflow

This is needed in order to run git describe --tag

d696e2b48594bc527cd011c2022820e934c7e23a authored over 1 year ago by Jack Koenig <[email protected]>
[ExportVerilog] Add disallowArrayIndexInlining option (#4706)

Add an option to disallow the inlining of expressions into the index of
array get and slice ope...

15a1f95f2d59767f20b459a12ac42338de22bc97 authored over 1 year ago by Fabian Schuiki <[email protected]>
[LowerAnnotations] Allow wiring type-equivalent types.

Fixes #4651.

c121a67ba73c464580be92ef2b7f957b7b673a43 authored over 1 year ago by Will Dietz <[email protected]>
Improve MacOS published binaries and flow (#4701)

* Disable ZSTD so that MacOS binaries do not dynamically link against
libzstd
* Use install ...

aadb930c9db776cb1c546ab87e9159127154fb3f authored over 1 year ago by Jack Koenig <[email protected]>
[ESI] FIFO0: fixing misnamed port

Input FIFO0 channels produced `_ready` in the output ports during
lowering. Should have been `_r...

eb0967539586cde267ba53a28c706b32b1074a63 authored over 1 year ago by John Demme <[email protected]>
[LowerToHW] Reduce dontTouch+zero-width error to warning. (#4703)

This is apparently used, continue to remove despite the annotation,
but issue warning.

ded84fa00b780405cf1511a4e03e180d5a3cc0eb authored over 1 year ago by Will Dietz <[email protected]>
[FIRRTL][FoldMemRegs] Fixups to avoid memory safety issues. (#4702)

Fixes two ASAN reported errors:
* erasing while iterating over uses
* don't use `.getDest()` o...

25997f6be3c91888014de19831574b8d1c2f9f7a authored over 1 year ago by Will Dietz <[email protected]>
[COMB] disable one folder for 25% end-to-end perf improvement. (#4690)

ExtractOp has a canonicalizer which uses computeKnownBits. This canonicalizer is very expensive...

263ce5a645070e9d780976c228d74cddf0df0c5c authored over 1 year ago by Andrew Lenharth <[email protected]>
[Handshake] Fix incorrect operation deletion in EliminateCBranchIntoMux canonicalization pattern (#4650)

This fixes a bug in the `EliminateCBranchIntoMuxPattern` canonicalization pattern where a `cond_...

083de301f0affa73d2c7f59ea73dbd03acd57bb6 authored over 1 year ago by Lucas Ramirez <[email protected]>
[Arc] Add dialect (#4681)

Add the `Arc` dialect which is useful for capturing a canonical
representation of the state tra...

037bd2b012c846e3f3cd67b7203bb8cfbf34b169 authored over 1 year ago by Fabian Schuiki <[email protected]>
[CombFolds] Propapate bin flags through icmp and variadic op canonicalizer (#4695)

This commit propgates bin flags through icmp and varidic op canonicalizer.

* `icmp bin eq 1, ...

c093eeb6f769674b53d4e4d5aa03579e492ca2cb authored over 1 year ago by Hideto Ueno <[email protected]>
[ESI] Initial FIFO signaling: read latency 0 style (#4679)

Teach ESI about FIFO signaling with a read enable latency of zero. Doesn't support buffering or ...

3bf847c08671e47428a67532389d60c930921efd authored over 1 year ago by John Demme <[email protected]>
[ESI] [mostly NFC] Lower ports pass refactoring (#4670)

Hopefully this refactor will 1) be more robust and rely less on implicit rules and 2) be more am...

2386315bde2930858ca9457d09a43eface96e556 authored over 1 year ago by John Demme <[email protected]>
[MemOp] Replace single-address memories with registers (#4687)

This pass replaces single-address memories with one register.
The write ports are ordered and i...

9770db4914a5bf1e289cf3639f87706916f0195e authored over 1 year ago by Nandor Licker <[email protected]>
[LowerToHW] Handle port dontTouch, add inner sym. (#4675)

Ensure DontTouched ports have symbols on them to model "don't touch", consume the annotation.

...

d4c7f19125d3859d86d1726b1f5d77a431ece3ef authored over 1 year ago by Will Dietz <[email protected]>
[FIRRTL] Limit BitCast to passive output, fix non-passive input. (#4648)

1088c796a668934a2debb57515f6e8bb203bf840 authored over 1 year ago by Will Dietz <[email protected]>
Revert "Revert "[HW][NFC] Modify ports shouldn't touch the body block""

This reverts commit ad55a2080167f8ea1b1e6593064b1aa9f212e2e4.

This reverts a revert which broke...

42ea52a8412294898b6907870ce47e55dcf101c4 authored over 1 year ago by Andrew Lenharth <[email protected]>
Revert "[HW][NFC] Modify ports shouldn't touch the body block"

This reverts commit e31e7f2e77d300259555b89b980895eacb689261.

Adjusted the comment to indicate ...

ad55a2080167f8ea1b1e6593064b1aa9f212e2e4 authored over 1 year ago by Nandor Licker <[email protected]>
[MemOp] Fix used bit range search in FoldUnusedBits

c5f4f77b915216717dad20d90133ba5b9ce00e3c authored over 1 year ago by Nandor Licker <[email protected]>
Fix Combinational Component Builder (#4680)

502bd451c3ef9acfa126d281cab5a376ceb0b1a1 authored over 1 year ago by Andrew Butt <[email protected]>
[NFC] Whitespace fix

8e911fa3c653739c60067ba663f6a07721f1f04e authored over 1 year ago by Fabian Schuiki <[email protected]>
[circt-reduce] Steal CIRCT_DIALECT_LIBS from circt-as

Instead of listing all dialect libraries manually, query the list of
registered dialect librarie...

bb1236fb28fc5d020a21415c0af6685f04db3734 authored over 1 year ago by Fabian Schuiki <[email protected]>
[NFC] Remove empty comment

d52e9f4c9ba2bcbd7f4799b9aca861988cf34035 authored over 1 year ago by Fabian Schuiki <[email protected]>
[MooreToCore] Add missing static keyword; NFC

Without this we may end up generating conflicting symbols if other
conversion passes also declar...

436a2547b6a37a2fae0ae125afd03d58ac476c5d authored over 1 year ago by Fabian Schuiki <[email protected]>
[LowerAnnotations] Make DUT module public (#4672)

This changes LowerAnnotations to make the module visility public. DUT interface is intended to b...

335f53df93d5e96a224e2e3667ec995491314e3f authored over 1 year ago by Hideto Ueno <[email protected]>
silence warning (#4678)

4c1f0b4ee84a72760e0dba6822ae13ffb52692ff authored over 1 year ago by Andrew Lenharth <[email protected]>
Handle all data-flow ops in FieldSource (#4673)

cf2ea58e19d19181aab53977d1de390135aeff48 authored over 1 year ago by Andrew Lenharth <[email protected]>
[cmake] Tweak suggested release tags, suggest firtool over sifive. (#4676)

60d4c5115d07197ba1b4107a8c213217c1a51c2f authored over 1 year ago by Will Dietz <[email protected]>
Silence Warning and fix analysis preservation.

0b226442cd490829bcd22df1f75cf9357f2bc29f authored over 1 year ago by Andrew Lenharth <[email protected]>
[HW] Add a canonicalization to swap constant index and unknown index of array gets (#4668)

This implements canonicalizer to sink constant index to inner array create.

```
array_get c...

f4a12353a7a084b9a69803b4b2f5ebae08e1389a authored over 1 year ago by Hideto Ueno <[email protected]>
Bump LLVM to top-of-tree

Signed-off-by: Schuyler Eldridge <[email protected]>

dfbb173faa004dd2f0cd528a1df69cd3b7f95049 authored over 1 year ago by Schuyler Eldridge <[email protected]>
[FIRRTL][LegacyWiring] Fix insertion point for fieldID. (#4664)

Fixes #4663.

6d043ddc374cc1e487ec928e2d20e0fc3d878de2 authored over 1 year ago by Will Dietz <[email protected]>
[PyCDE] Expose new pure module input/output ops

6d81734c610d527722964369da97ba88cef99d9a authored over 1 year ago by John Demme <[email protected]>
[MSFT] Support `msft.instance` in non-MSFT/HW modules

Lowering `msft.instances` required the `__INST_HIER` parameter to exist,
so when lowering inside...

52d989755defdea00fde12b5a4b0db215538bc8c authored over 1 year ago by John Demme <[email protected]>
[ESI] Lower pure modules into HW modules (#4658)

Implement a lowering which converts `esi.pure_module`s into `hw.module`s. Uses the `esi.pure_mod...

dc8cdc03308f1bd17dae84e1e469a54621d6ce69 authored over 1 year ago by John Demme <[email protected]>
[ESI] Run the service generators in HWModuleLike

Modules which implement HWModuleLike can run service generators. We only
need the mutability to ...

80f59df265e288bba390e36ff32055c59d3a8e48 authored over 1 year ago by John Demme <[email protected]>
[ESI] Make ESIPureModuleOp implement HWModuleLike

73cd4d915445a6bd1a6c65e6e36d7d020cf31174 authored over 1 year ago by John Demme <[email protected]>
[PyCDE] Fix debug logging

Dumping the IR after every phase was wonky.

0d2bfa7d83af82ebcbd7b58bed3fb189c1aa012a authored over 1 year ago by John Demme <[email protected]>
[ESI] Introduce `pure_module.input` and `pure_module.output` (#4657)

These ops are intended to be produced by service implementation generators to translate service ...

5ae8a5f7be478ea3185b63ed7f0be2a488bea50b authored over 1 year ago by John Demme <[email protected]>
[CheckCombCycles] Iterative Tarjan's SCC to detect cycles (#4642)

Re-implement the pass using an iterative Tarjan's SCC algorithm instead of the
current recursiv...

535def1265e7ed406a1dc2cbfbc484d540f6e4e4 authored over 1 year ago by Prithayan Barua <[email protected]>
[PyCDE] Remove dead code

The PASSES field of System was replaced by PASS_PHASES some time ago.

deee49ba150cb73cbe7d084cef7ba73457de3fc5 authored over 1 year ago by John Demme <[email protected]>
[PyCDE] Add `bit` type for convenience

Save users some keystrokes for a very common type -- a single bit.

bd4e0095736ba195d897439367252676d9e3b255 authored over 1 year ago by John Demme <[email protected]>
[ESI] Add specification to build signals into SV interface or not (#4653)

Support both modes wherein external modules' signaling are bundled in SV interfaces and just app...

11496189177d74b0b4c041790736658785be98d6 authored over 1 year ago by John Demme <[email protected]>
[LowerTypes] Track public modules and lower ports properly (#4655)

This changes LowerTypes to look up module visibilities. `module.isPublic()` cannot be called fro...

b16d03ff3416d31f5bb3fefa965ed4b5596d4a30 authored over 1 year ago by Hideto Ueno <[email protected]>
[FIRRTL][MemOp] Removed unused bits from memories (#4652)

cc1a5ee8e8439ea3d10b766da6643bc2a42507ab authored over 1 year ago by Nandor Licker <[email protected]>
[HW][NFC] Modify ports shouldn't touch the body block

As per the [documentation in
HWOpInterfaces.td](https://github.com/llvm/circt/blob/a054073460650...

e31e7f2e77d300259555b89b980895eacb689261 authored over 1 year ago by John Demme <[email protected]>
[HW][NFC] Add `getPorts` to HWMutableModuleLike op interface

As part of this addition, I moved `ModulePortInfo` and all of its
dependent structs/enums to HWO...

a054073460650f3192a05cf4c1142e2a049da9c6 authored over 1 year ago by John Demme <[email protected]>
Bump llvm (#4645)

2efe829467d430e7104b3f3ecf6a96243e161a88 authored over 1 year ago by Robert Young <[email protected]>
[ESI] Add signaling standard to channel type

In the past, ESI has only supported valid-ready signaling, so we didn't
need to encode the signa...

333860934157f5b51c7a3d5fdfd45b391c44d350 authored over 1 year ago by John Demme <[email protected]>
[FIRRTL] Simple points-to like analysis (#4637)

This analysis maps values back to their definitions (operations which produce a new value) and p...

db40efbcdc7275df4ba67dd455a53f5342ae1ce4 authored over 1 year ago by Andrew Lenharth <[email protected]>
[FIRRTL] Fix missing BlackBoxPathAnno Lowering

Add a known and supported annotation to the LowerAnnotations Annotation
table. This was acciden...

0285a98d96b8df898e02c5ed9528f869bff80dcf authored over 1 year ago by Schuyler Eldridge <[email protected]>
[NFC] spelling

ffa319f9bdc253c524f69e995ac6ec6f7e483b19 authored over 1 year ago by Andrew Lenharth <[email protected]>
[FIRRTL][AddSeqMemPorts] Fix use of DenseMap entry after invalidated. (#4643)

abdc30da6f7df3e2afbecc9c01f0c06f2173b554 authored over 1 year ago by Will Dietz <[email protected]>
[firtool][NFC] Test relative path includes. (#4641)

Test that resolving using relative include directories works, and check behavior re:search order...

78495fb266b1cfe9931e51b53d1ac5bf67fe8a45 authored over 1 year ago by Will Dietz <[email protected]>
[SV][ETC] Name port after instance.result_name, as well. (#4640)

Fix case where port is named "" (_GEN), teach to grab name from instance.

Add test based on c...

d87ebfa0f37c126b24a722ae2ea2092c60148902 authored over 1 year ago by Will Dietz <[email protected]>
[ESI][Cosim Runner] Add support for running binaries (#4639)

Adds the '--exec' flag to tell this util to run the file instead of
parsing it and constructing...

14bb38c7595e6b380462eef9575793ed16391710 authored over 1 year ago by John Demme <[email protected]>
[PyCDE] ESI pure module entry (#4635)

Teach PyCDE about ESI pure modules.

28c132d1ccdffee0650799d0069b50edd1fab2ab authored over 1 year ago by John Demme <[email protected]>
[ESI] Introduce ESI pure module op (#4633)

A module containing only ESI channels and modules with only ESI ports. All non-local connectivit...

f50b5c737f7e6bfebceaa3e81ce9fd1d47a10f4b authored over 1 year ago by John Demme <[email protected]>
[FIRRTL] Improve BoringUtils Names (don't use pin)

Change the way that BoringUtils-backing infrastructure creates wiring
problems to not suggest a ...

fef7ca7d30e3a2a49ddfe6ad2fbd48da7cda5289 authored over 1 year ago by Schuyler Eldridge <[email protected]>
[Docs] Update Python example, NFC.

5d8abac0f503148b0a68a7c8c801acf7a4715907 authored over 1 year ago by Mike Urbach <[email protected]>
[FIRRTL] Don't Remove File-init Read-Only Memories

Block removal of read-only memories that are initialized via a file.
This is a common FPGA ROM p...

203b78283b5f09eaadc510e56a939698a0856a4f authored over 1 year ago by Schuyler Eldridge <[email protected]>
[FIRRTL][NFC] resize SmallVectors to hold at least initializer.

Size to largest size they might take since only a few more.

508a885cb426e4cf0d63afaf2f948d810533e794 authored over 1 year ago by Will Dietz <[email protected]>
[HWLegalizeModules] Legalize aggregate constant (#4626)

This PR extends HWLegalizeModules to support aggregate constants.
Also `signalPassFailure` is ...

2b612a2dcd1cc0eeb91dcbcfc0cb288f77f20ff3 authored over 1 year ago by Hideto Ueno <[email protected]>
[LowerAnnotations] Resolve legacy wiring annotations as WiringProblems (#4496)

Resolve legacy wiring annotations as WiringProblems.

Support Chisel BoringUtils.

05ca6572e0a4962599cdb0f21cdc81dd9f4d86fb authored over 1 year ago by sam-shahrestani <[email protected]>
[FIRRTL] Chisel Memory File Init Integration Tests

Add an integration test of Chisel features for loading memories:

1. loadMemoryFromFile
2. l...

694a3e2a599ef76ff224d8f1580a5ffc75a4a1f5 authored over 1 year ago by Schuyler Eldridge <[email protected]>
[HWMemSimImpl] Add Memory File Initialization

Add support to HWMemSimImpl for doing file-based memory initialization.
This comes in two flavor...

b6dd1c3ecd72972d32511592e4dccf3beb455e67 authored over 1 year ago by Schuyler Eldridge <[email protected]>
[LowerToHW] Whitespace Cleanup in Test, NFC

Signed-off-by: Schuyler Eldridge <[email protected]>

c1601ec84597f11ea5e626a4c68e1a843877eeef authored over 1 year ago by Schuyler Eldridge <[email protected]>
[LowerToHW] Add Memory Initialization Support

Add FIRRTL memory initialization via file support.

Signed-off-by: Schuyler Eldridge <schuyler.e...

a8bb279d48555f2977277c09215c31c2281e7d63 authored over 1 year ago by Schuyler Eldridge <[email protected]>
[FIRRTL] Add Memory Initialization to FIRRTL Infra

Add Memory Initialization information to FIRRTL pipeline infrastructure.
This information is dro...

822da7fcbe5bc6a389669a18e001916cc5945752 authored over 1 year ago by Schuyler Eldridge <[email protected]>
[FIRRTL] Add Memory Annotation Parsing

Add parsing of the two memory initialization annotations which implement
the Chisel loadMemoryFr...

b387c034f022d50264460a622c464dbf3be050a6 authored over 1 year ago by Schuyler Eldridge <[email protected]>
[FIRRTL] Add MemoryInit to CHIRRTL memories

Add a MemoryInitAttr to CHIRRTL memories (CombMemOp and SeqMemOp) to
record information about fi...

8a2d2bb83d9b394a80e1e710c10aa4f14a69da75 authored over 1 year ago by Schuyler Eldridge <[email protected]>
[FIRRTL] Add MemoryInitAttr to FIRRTL Memories

Add an optional attribute of type MemoryInitAttr to FIRRTL's MemOp in
order to capture external ...

20e30e2cded2ba486ea314112eb078435031e86b authored over 1 year ago by Schuyler Eldridge <[email protected]>
[FIRRTL] Add MemoryInitAttr

Add, but do not use a dialect attribute, "MemoryInitAttr". This is a
single attribute that repr...

f107478939b6d7feef47c7dea9a56aedffaa0f25 authored over 1 year ago by Schuyler Eldridge <[email protected]>
[ESI] Baseline XRT support (#4537)

Adds a "BSP" for XRT which just sets up the infrastructure. Outputs the "build package" complete...

6952f64cb91e06d357bb580fb04617b3198f1e1b authored over 1 year ago by John Demme <[email protected]>
[FIRRTL][SV][SystemC][ESI] Remove extra whitespace around optional attr dicts (#4324)

Often, we unconditionally print a space before printing optional attribute
dictionaries. Howeve...

32f3efe1d4219483c797305def8af642115c75f1 authored over 1 year ago by Robert Young <[email protected]>
[firtool] Use CIRCT's StripDebInfo pass instead of upstream (#4632)

With the recent change to how port location information is handled, the
upstream pass StripDebu...

601b33bcdaa4406ae925d25d2e46671808a1bd6a authored over 1 year ago by Andrew Young <[email protected]>
[ExportVerilog] bindfile is a sv file and should be marked as such

d65914cd88b8342fe69797fcc34dea14ac07a210 authored over 1 year ago by Andrew Lenharth <[email protected]>
[FIRRTL][NFC] Remove unused port boring/LCA methods. (#4630)

90b1bc50d4a26e62a475133c1fd5ca3b47b1837e authored over 1 year ago by Will Dietz <[email protected]>
[ExportVerilog][PrettifyVerilog] Fix exprInEventControl (#4625)

This commit fixes bugs in spilling logic regarding expressions used in sensitivity list.

* Pr...

0e70371b2c5b4ad90fea4ba84a14a29615ab26f7 authored over 1 year ago by Hideto Ueno <[email protected]>
[HW][NFC] InnerRef: Remove unused method definition from dropped inteface. (#4629)

No longer implement the SubElementAttrInterface interface,
so this method is no longer useful.

830d4ed6e7e47aa41600ccc92a439fd25e1a0fa4 authored over 1 year ago by Will Dietz <[email protected]>
[GC] Update numXMRs statistic. (#4628)

Fixes #4542.

da4a2072e4b46cf74f47ff583a08a05d089619ea authored over 1 year ago by Will Dietz <[email protected]>
[CHIRRTL][NFC] Indicate using new fold API to squelch warnings. (#4627)

No folders to update, but explicitly move to new fold API.

5125b035ff8b7c2d6ef3441ce3b2347c2e17e8af authored over 1 year ago by Will Dietz <[email protected]>
[ExportVerilog] Return empty string if location is empty

This fixes an issue introduced by 92011d that an empty location is emitted
when a lowering optio...

c7767562b6bc5a27c757581c44f4c4aa611e8adb authored over 1 year ago by Hideto Ueno <[email protected]>