Many CIRCT frontends don't generate clean HW representations of their
inputs, but instead inter...

Add the `MakeTables` pass which finds small arcs and converts them into
a lookup table where po...

Add the `SinkInputs` pass which sinks constants into arc definitions
where possible. The arc co...

Add the `SplitLoops` pass which splits arcs with multiple results into
arcs with just one resul...

Lower `firrtl.node` ops to the new `hw.wire` which is pretty much a
one-to-one lowering.

Add support for the new `hw.wire` op to ExportVerilog. More specifically
this commit makes Lega...

Add the `hw.wire` operation to the HW dialect. A wire offers the ability
to assign a human-read...

Move the `{parse,print}ImplicitSSAName` directive currently used by the
SystemC dialect into th...

Revert a mistake from earlier tonight.

Add an output directory in the `unittest` decorator to avoid `System`s
writing to the same outpu...

pypi doesn't accept non-auditwheel'd packages. So we must exclude the
collateral objects instead...

This PR removes many hidden developer options from `firtool`. These
options were more useful w...

Currently the `lowerAlwaysInlineOperation` function will happily move
ops right in front of the...

Factor the lowerings for `SubindexOp`, `SubaccessOp`, and `SubfieldOp`
out into dedicated `lower...

Add a builder which accepts the `field` name as a `StringRef`.

This fixes the CI failure in c578e6ec

* Bump LLVM, fix mergeBlockBefore -> inlineBlockBefore

* Removed deprecated APIs

* Update ...

Necessary to synthesize and simulate ESI systems out-of-tree. Had to refactor some CMake files t...

* [FIRRTL][InferWidths] Honor upper bounds on AttachOp

Fix an issue in `InferWidths` where an...

Use the recommended GitHub action for this given on
packaging.python.org. Include the PyPI API t...

Fixes build on some configurations (here, gcc 12.2+libstdc++).

Error in template bits starting ...

Add the `arcilator` convenience tool to make experimenting with the
dialect easier. The intende...

Add the `InlineModules` pass which forcefully inlines all private HW
modules. This essentially ...

Add the `Dedup` pass which deduplicates arcs with identical definitions.
If arcs differ only by...

Instead of checking for `isPure` on arc body ops, which includes a check
for `isSpeculatable` wh...

These tests were poorly behaved

- Include capnp, kj libs in PyCDE cmake 'install'
- Use 'install' to build the wheel

This test revealed #4807. Changing a module name as a mitigation.

Reference don't behave quite like normal types, so don't use the same connect operation on them....

Updated XRT BSP and didn't update the test. Oops.

This reverts commit 3ddf879a1ec339735174d735e0414865278c990e.

Neither of these are safe if the ...

Add method to generate a new InnerSymAttr with the specified field's inner
symbol removed.

Add method for setting all inner symbols at once, using the provided
InnerSymAttr, not just the...

Add a missing verifier to the attach op that checks that all known
widths of operands must match...

There is a bug that implicit ext/trunc of reg reset's reset values is not handled in RegisterOpt...

Virtually NFC, cleanup a common pattern with a helper function.

Replace instances of:

```c...

Appease the clang-tidy.

Rename inferUnaryReturnType's first parameter to 'input'
to match the m...

Don't recurse on def-use chains.

This function does not appear to be used, FWIW.

Make IMCP not try to optimize registers. All the existing firrtl register optimizations are unsa...

Detect the 'module' string being parsed as `kw_module` instead of `identifier` when it's used as...

Since all hardware types will be able to be 'const', previously buildable types
will no longer ...

ModuleNamespace was used by multiple threads and was walking modules
for every memory within.
...

This fixes a crash in isDuplicatableExpression when array index is a port or read of a port.

Add FIRRTLValue, FIRRTLBaseValue conveniences, use a little.

Narrow SubindexOp/SubaccesOp to ...

Change the MemToRegOfVec pass to work on all memories (which match its
filtering criteria) if th...

Remove the "tb_seq_mems.json" metadata file as this has not been used
for a long time. This was...

The FIRRTL and SV dialects have an almost interchangeable implementation
of the `ImplicitSSANam...

Especially since this is likely our bug if encountered.

This check is already covered in the as...

This commit adds `cl::AddExtraVersionPrinter` to circt-opt as we are doing
in firtool.

Fix a bug in CreateSiFiveMetadata where global state is not cleared
between invocations of "runO...

Fix an issue introduced in 81966c0ac that affects the ArrayGetOp Python
binding.

The `ArrayGetOp` has a `TypesMatchWith` constraint which ensures that
the result type of the op ...

Signed-off-by: Schuyler Eldridge <[email protected]>

This was removed in b6d8508ba104b3120965dc031a3edfd538fb4602 .

InstanceOp is "special" in that the inner symbol targets
the instance itself and its results ca...

This commit tries lowering firrtl subaccess operation into SV variable
index assignment when po...

1) Collapse a trivial ref.resolve of an ref.send:
ref.resolve(ref.send(x)) -> x

2) Hoist ref...

Fix incorrect behavior for SiTest BlackBoxes when the
firrtl-emit-metadata pass is run without a...

1) Don't dereference op after checking if it's null.
(shame compiler doesn't see through thi...

Encountered through InferWidth's debug prints.

Ensure code continues to work for anything that's FConnectLike,
without having to add it to eac...

https://github.com/llvm/circt/commit/c4447004c344e5a3391a1d7546565197a7dd324f causes a width mis...

Implements a very basic XRT register MMIO space. Has the ESI magic number and version number.

Perform vb->bv conversion before flattening memories. The vb-to-bv pass cannot
reshape memories...

- Different function signature for running the PassManager.
- No longer require SVAttributesAttr...

Only change on our side was to Python integration tests, which needed a small tweak to `pm.run` ...

My initial understanding of memory latencies was incorrect and I wrongly inserted pipelining aft...

This fixes nondeterminism caused by iteration over DenseMap. Instead use MapVector to guarantee ...

GCC+debug consumes too much memory. This swaps gcc and clang build mode.

CI: https://github.c...

Rename the `disallowArrayIndexInlining` lowering option to
`mitigateVivadoArrayIndexConstPropBu...

* [SV] Move emitAsComment to SVAttributeAttr; remove SVAttributesAttr

Move the `emitAsComment...

This pass converts objects with the shape vector<bundle> to bundle<vector>.

These will in the short term replace the intrinsic annotation. This initially only adds represen...

This aligns the package name to the module name in the code.

This will be `pip install circt`, ...

Some external modules use unusual port naming conventions. Since we want
to avoid users needing...

Used to avoid warnings and in situations where other code has messed with the `default_nettype`.

This commit moves FirtoolPassInstrumentation to a support header and rename FirtoolPassInstrumen...

Disable memory folder to deal with #4734

Not presently reachable, but if a reference type is parsed
print error on parssd tokens not, e.g...

Only minor changes needed on our end:
* circt-translate: Update test to reflect supporting mult...