[Handshake] Make ControlMergeOp idx result AnyType

This commit changes the type of ControlMer...

Test introduced in #4815.

1) CHECK-DAG-SAME doesn't exist/work.
2) Test check line was wrong an...

Check for failure and propagate.

https://reviews.llvm.org/D146785

On the path to supporting forcing declarations, we want to be able to differentiate whether a re...

Builds with LLVM_ENABLE_THREADS=OFF were broken in the last llvm commit. Fixed by https://github...

This reduces entire execution time by 2~3%.

Close https://github.com/llvm/circt/issues/4867

This improves IMDCE by managing instance live...

We previously extracted instances that only feed the test code. This
change enhances that logic...

Fix an issue where lit tests that were expected to crash would take a
long time to finish (possi...

Move all functions pertaining to Field IDs from being declared only on
FIRRTL Types into the pre...

And change the others' module names to `OrInts` to match with the
functionality.

Add regression test.

Add folders for aggregate create operations:
```
vector_create(%foo[0], %foo[1]) -> %foo : ve...

Add "define" statement from FIRRTL 2.0, move all reference connections to use this.

Update pa...

This commit fixes tow issues:
* Async reset registers are not initialized with "disable-registe...

Tap sink must be passive.

* Add stable attribute to booleanAttr

* add other component attributes

These are now supported as of #4801.

Add basic parse test, drop negative test.

Use to simplify some cast chains involving getBaseType.

Per Reference Types FIRRTL proposal.

Note this is not reachable yet, just loosening the restr...

Map to current IR constructs.
* Using connect/refconnect instead of define (let emitConnect han...

Add an operation to represent leading and trailing zero counts. These
operations are commonly su...

After the muxes that represent enables and resets are factored out by
the `InterStateProperties`...

A pass to detect resets and enables in arcs. Making them explicit allows
another pass to pick th...

Add two passes to lower a design to a software model.

The `LowerClocksToFuncs` pass outlines ...

Dump operands (Value's, since that's all we need) into a SmallVector, to
workaround issue with ...

Add three passes that implement state allocation. The passes take the
abstract state allocation...

I'm saying bye-bye to my fancy templates in favor of a fully generic solution.
All operations (...

A 'data window' allows designers to break up large messages into multiple
frames (aka phits) sp...

Add a `createTmpHWWireOp` similar to `createTmpWireOp` that creates a
throw-away `hw.wire` whic...

Lower `firrtl.wire` ops to `hw.wire` instead of `sv.wire`. The change is
fairly mechanical: ins...

Simplify the `lowerRegConnect` function such that it rejects subfield,
subindex, and subaccesse...

Co-authored-by: Prithayan Barua <[email protected]>

* Change Upload Binaries to Upload Firrtl Binaries

This vastly reduces the size of the upload...

Fixes #4889.

This adds operations for defining Classes and their Fields, according
to the design in the rati...

Add the `LowerState` pass and accompanying operations to convert a
design from a pure state tra...

Adds some updated markdown docs and some basic examples. Not complete, but a start.

* [CalyxToHW] Support multiple guarded assigns to the same destination

According to the Calyx...

Python has a syntax for creating lists with the * operator. Use that
same syntax in PyCDE. Inten...

If name isn't specified, set the system name to something better than
"PyCDESystem".j

Missing deps meant that `pip install pycde` resulted in incomplete
install.

Small touchup to code updating NLA's.

Handle ports, extmodules, and per-field symbols in InnerSymDCE.

Add FIRRTL-only support for s...

The `InferWidths` pass currently errors out if the input contains any
`InvalidValueOp`s that ar...

Add a canonicalizer to remove `InvalidValueOp`s without uses.

A tab snuck in.

We haven't set up the proper metadata yet, so disable the workflow
from running `twine check` un...

Rearrange constants in concatination strings to enable constant merging.
Eliminate double inver...

Narrow simple logical ops when possible.

Also remove redundant pattern for 2-deep muxes. Removing this showed the backwards logic of the...

* LLHDToLLVM: make void pointers consistent

---------

Co-authored-by: Martin Erhart <maerh...

This is simple and only considers identity on mux conditions. A more complete solution would loo...

This PR removes output ports with no user. Close https://github.com/llvm/circt/issues/4156. Mayb...

Narrow add and sub operations.

Fix InferResets dumping the entire module when it hits an uninferred
port. Improve the existing...

Use `std::function` for the `notifyOpErasedCallback` instead of
`llvm::function_ref`, since we w...

Fix an issue with the windows build introduced in e45cd550f.

Our llvm-lit arguments default to `-sv`, which makes the output succinct
and nice for interactiv...

Only LPKEYWORD_PRIM's should be handled as primitives.

Add test where a printf used as an exp...

This PR adds a section `Recommended LoweringOptions by Target` to verilog generation doc.
As Ch...

Fix an issue where `pruneUnusedOps` would remove operations that the
overall `circt-reduce` driv...

This defines the dialect boilerplate, as well as a rationale document
that explains the intende...

Fix a source of crash in `circt-reduce` where the tool would try to
apply a reduction to a pare...

This makes IMCP field sensitive. Previously lattice values were associated with `Value` but this...

If the read latency is 1, Vivado issues a warning since the behaviour under a collision
is unde...

* Fixup cases with trailing or leading arrows.
* Fix printing starting value twice, misrepresen...

Method name was duplicated, and unused.

If func::FuncOP argument attributes/results have the "calyx.port_name"
Attribute, use it to set...

Add an `arc.tap` operation that allows us to assign a name to an
arbitrary SSA value such that ...

Don't ignore parameters builder argument, add support for specifying
internalPaths during build...

Add an experimental pass to convert operations in the Comb dialect to
their equivalent in the A...

Add a pass that inlines all arcs with only one use or with a trivial
number of operations in th...

Add the `arc.lut` op which groups combinational ops in its body for
later conversion into a sim...

Add the `RemoveUnusedArcArguments` pass that does exactly what it says.

Co-authored-by: Marti...

Add the `SimplifyVariadicOps` pass which takes the common combinational
operations and converts...