Fix a bug in the SFCCompat pass where only top-level operations in a
module were walked. This r...

Only check during parsing to stay compatibile with previous behavior.

Allow abstract reset on...

Add support for wrapping Ibis classes with ESI in PyCDE. These wrappers are temporary until Ibis...

Exclude the `ImportVerilog` tests from the nightly valgrind runs, as
they uncover a "Conditional...

We have a centralized emitConnect helper that knows how to create the
right kind of connections...

Move the call to `registerFromVerilogTranslation()` from the
`InitAllTranslations.h` header, whe...

Add an `--import-verilog` translation target for `circt-translate`. This
facilitates writing si...

Fixes a crash when compiling a Chisel read only memory with a LoadMemoryFromFile annotation usin...

Deal with a few more situations when outputting chisel interfaces.

Cleanups which have been accumulating and are mostly unrelated to
a new feature.

This is a straightforward 1:1 conversion from FIRRTL IntegerShrOp to
OM IntegerShrOp, using the ...

This op shifts its lhs OMIntegerType operand right by the rhs
OMIntegerType operand to produce a...

This adds parser support for IntegerShrOp by defining the primitive
expression keyword. This is ...

This adds parser support for IntegerMulOp by defining the primitive
expression keyword. This is ...

This op multiplies two OMIntegerType operands to produce an
OMIntegerType result. This defines t...

This op shifts an FIntegerType lhs operand to the right by an
FIntegerType rhs operand. This def...

This is a straightforward 1:1 conversion from FIRRTL IntegerMulOp to
OM IntegerMulOp, using the ...

This op multiplies two FIntegerType operands to produce an
FIntegerType result. This defines the...

This adds support for the Evaluator to evaluate integer binary
arithmetic. This is defined in t...

This is a straightforward 1:1 conversion from FIRRTL IntegerAddOp to
OM IntegerAddOp, using the...

Fix a bug in the LowerLayers pass where operations with inner symbols
inside layerblocks would n...

Change files generated by the LowerLayers pass to use a "layers_" prefix
and not a "groups_" pre...

Remove a duplicate setting of the location when parsing enum expressions.

Signed-off-by: Schuyl...

Change the 'parseEnumExpr' to create a const zero-width zero and not a
non-const one. This alig...

Fix a bug in zero-width enum parsing that arose because the location was
not set. This would ca...

MLIR fails to separate enums by dialect, thus including a `.td` file which defines in another re...

Fix more hold-overs from when input and output were split.

See #6707

Also mark modifyModulePorts as deprecated as it is input/output relative.

See #6706

This op adds two OMIntegerType operands to produce an OMIntegerType
result. This defines the ev...

When lowering object instantiations, we need to get the source from a
propassign to pass that V...

We don't need to copy APSInts for the arguments in this interface
method, and in fact clang-tidy...

Major change in FIRRTL 4.0.0.

---------

Co-authored-by: Schuyler Eldridge <schuyler.eldrid...

Fixes: #6694

ImportVerilog.cpp depends on header files which are generated during the build of the slang_slan...

This adds parser support for IntegerAddOp by defining the primitive
expression keyword. This is...

Specify fget in the port class itself to that users still have access to the port's properties t...

As we start adding integer binary arithmetic expressions, this will
allow us to abstract over t...

This adds some basic rationale for why it is valuable to be able to
represent computation in th...

This op adds two FIntegerType operands to produce an FIntegerType
result. This defines the usua...

This is currently always defining the inferReturnTypes method from
InferTypeOpInterface on all ...

These currently default to calling emitError(), which uses the current
token's location. In som...

On modules we keep an array attribute `port_locs` for port location
information. On regular HWM...

Also renamed `targetNames` to `caseNames` to better match the FIRRTL-level terminology

The previous fix in https://github.com/llvm/circt/pull/6572 did not
get to the root of the issue...

* Change isMovableDeclaration to allow operations to be lifted if all their operands are constan...

To accomodate upcoming slang 4 builds. Changes the version of clang in
the integration tests to 16.

Updates to LowerLayers to support driving layer-associated probes.

Signed-off-by: Schuyler El...

This test was added with a small patch recently, but the test didn't
really check anything beyon...

The previous logic would create classes for any FIRRTL modules that
had property ports. However...

Co-authored-by: Mike Urbach <[email protected]>

* PrintStateInfo refactoring

* remove printinfopass

* fix failing tests

* extract arcil...

Make `ImportVerilog` honor the `singleUnit` option by either adding all
source files to a singl...

Fix an error if a 0-bit was shifted right by any amount and this made it
all the way to LowerTo...

A hidden command-line argument is added to re-enable the pass on possible backports or during th...

Emit public FIRRTL dialect modules with the "public" keyword. This brings
the FIRRTL emitter fu...

Add some missing 'sstream' includes that were need on a fresh build on
macOS.

Signed-off-by: Sc...

Accept `EICG_wrapper` extmodules without `test_en` port in
`LowerIntrinsics`, and simply leave ...

Found via the (TIL) LLVM utility llvm/utils/filecheck_lint/filecheck_lint.py.

Fix support for refs into extmodule that's a public module within a separate circuit.

Prepare...

These are used in contexts that are not SymbolTables, so these cannot
be Symbols. It appears th...

The FullAsynchronousResetAnnotation is used to mark an asynchronous
reset signal in a module to...

Fleshing out support for standard services and addition to the manifest.

These are used in contexts that are not SymbolTables, so these cannot
be Symbols. It appears th...

This test appears to be testing ExportVerilog for a pattern that isn't
actually legal, since a `...

Also, ban capturing outer properties inside a layerblock.

Add missing requirements on slang for recently added circt-verilog
tests. This gets my local bui...

Add the `ImportVerilogOptions` struct to capture various options that
can be passed to the Slan...

This was unused. Fixes #6660.

Provide intrinsics to capture what today is encoded via printf + when/stop/verif-op pattern matc...

shared build seems to require a specific version of glibc and causes a build failure of downstre...

The enabled layers of a module act as requirements on the instance op--the
module may only be i...

rewriteModuleBody is ran parallely so we can ignore the overhead of
plain getFieldRefFromValue.

* [Calyx] Make ControlOp a SymbolTable.

During the Calyx control lowering, in an intermediate...

Since 5fb4cf5fd3a3dcaa05b43e340120ce9c3a75f597, ClassLikes are not
SymbolTables, due to the usu...

Conversions weren't actually counted, fix.

When checking the ops under a layerblock:

- When checking if an operand refers to a value def...

Fixes #6653 and adds functionality to test the fix.

Expand testcases from https://github.com/llvm/circt/issues/6608 to include uninferred widths.

Fix a few compilation warnings that sneaked through related to the
Instance Choice op.

Signed-o...