This API is useful when you have an Evaluator, but need to get back to
the core MLIR data struct...

Added a separate macro to bypass synthesis and enable initial blocks setting memories lowered th...

Co-authored-by: Nandor Licker <[email protected]>

Add a flat symbol reference attribute to OM dialect. This is required in
addition to the InnerR...

There is a use-case for CosimDpi.capnp in the tests and install, so
make sure to locate it prope...

Since the XrtBSP is in that dir, move into it to increase consistency.

A few issues:
- The new C++ API emission pass was choking on `test_esi.py` since one
of it's ser...

Wasn't installing the right runtime / build files into the pycde
package. Managed to get everyth...

For use w/deferred linking or the new ABI, ref statements
are not required. However, if they'r...

Ref-type ports on external modules should resolve to uses of the ABI macros when the path inform...

Fixes https://github.com/llvm/circt/issues/5231 .

Add regression test for macro formatting.

`ENABLE_INITIAL_REG_` is used to permit fine-grained control over register initializers.
It is ...

... progressive lowering of handshake!
This obviously requires a future addition of an `arith-t...

`dc.merge` will select one of the incoming tokens and emit an output stating which token was sel...

Signal a pass failure in addition to just emitting the error.

If a signal is annotated as the clock divider bypass signal, wire it to clock gates that have th...

* [FIRRTL] Const handling in cast ops

This commit adds a ConstCastOp for casting away constne...

There was a bug in LowerSeqToSV which creates invalid IR regarding dominance. Previously sv.arra...

* [FIRRTL] Handle flips in const connections

* Also fix a partial connect reset flip edge case

Support OpenVector, OpenBundle types.
Support OpenSubfield, OpenSubIndex, RefSubOp.

Add expo...

Phases separate the values in a firrtl program into two worlds, the property
world and the hard...

The Evaluator is responsible for evaluating the object model according
to the semantics defined...

Having SinkInputs as a rewrite pattern as part of ArcCanonicalizer allows to directly perform co...

It probably makes sense to add this single pattern to the new ArcCanonicalizer pass since it (1)...

On the HW/Comb level, the `comb.concat` operation is basically considered free. However, in simu...

To print debug info in MLIR output, the AsmPrinter CLI option mlir-print-debuginfo could be used...

Add a pass that allows us to implement canonicalization patterns that
require a symbol cache to ...

* [FIRRTL] Export named references as macros to Verilog files

---------

Co-authored-by: Hi...

Add the z3 include directories as system includes, not normal includes, to the
circt-lec tool. ...

* Remove the optional enable and clock operands from `arc.memory_read_port` making it a combinat...

Enumerations can only be connected when all variants, compared in order,
have the same name and...

There may be several files generated during any given run of firtool,
represented as sv.verbati...

Minor bump for small bugfix. Shouldn't break anything.

Adds option for controlling target line width (`--target-line-length=120`).

Add a canonicalizer that removes a "ref.resolve" of a "ref.send",
replacing this with the origin...

Signed-off-by: Schuyler Eldridge <[email protected]>

Currently, the Dedup pass only considers StateOp as call operations to arcs because this was the...

This adds a macro.decl to declare the existance and arguments of a macro.
This adds a macro.def...

This PR adds the DC dialect rationale and most of the dialect-related boilerplate.

$ can be used in the middle of the identifier so isValidVerilogCharacter should return true for $.

Add widthCastOp and resetCastOp to the FIRRTL emitter. These ops are
transparent no-ops that ar...

Add force, force_initial, release, and release_initial to the FIRRTL
exporter. This requires do...

Check forwarding up the hierarchy produces expected FIRRTL.

Update FIRRTL's emitter to support RWProbes.

Signed-off-by: Schuyler Eldridge <schuyler.eldridg...

* Parse mixed aggregates into open agg/sub ops.
* Run LOA after parsing (before LowerAnnotation...

Participate in inner symbol verification, data structures, and specify how per-field/target resu...

Keep the setCalleeFromCallable changes (due to MLIR change/improvement)
as defining them for now...

In particular, this caused a number of folder/etc users of this
method to erroneously believe t...

Check declarations have appropriate types before creation, and reject declarations of non-base f...

Immediately after parsing (cc #5128), "lower" the open aggregates containing mixed hardware into...

InlineArcs only considers arc.state operations at the moment. This adds
support to also inline ...

Implement the clock isolation into the clock_domain op that got added earlier. Implement an inte...

* Since `arc.storage.get` does not access the storage, but just adds a constant to the pointer (...

Update the FIRRTL exporter to support reference types (probe and rwprobe)
as well as probe, defi...

Open variants allow non-hw types within, and are themselves
not hardware types.

These are pl...

Removes the handshake to FIRRTL lowering pass.

Also:
* All handshake integration tests now r...

This will save us a few casts from FModuleLike to HWModuleLike.

Use same types for both sides, avoid uneven indexing.

Add test that crashes without this change.

Don't make assumptions beyond /usr/bin/env regarding the location
of various common utilities.
...

This implements some improvements to the circt-reduce infrastructure, fixes a few bugs, and adds...

Fix broken link to symbol rationale by pointing to hosted version instead.

This fixes two bugs in LowerMatches.

The first is when the match has no case statements, we w...