The motivation for this refactor is to:
* remove the entry block - there's a bunch of different...

This functionality isn't critical yet, so just disable the tests. Broken
by https://github.com/l...

Make `LowerToHW` emit `seq.firmem` operations for memories instead of
emitting generator ops. T...

Extend zero-width-ref pruning to handle Forceable + force/release ops,
and test nothing breaks ...

Chase to defining op, and (re-)index using ref.sub's.

Implementation:

Extend the refSend list node to support recording indexing
along the resolut...

This commit takes the ESI `ChannelRewriter` and generalizes it to provide a generic utility for ...

This PR modifies strictconnect's verifier/parser/printer to allow different (but structurally eq...

This avoids stack overflow when parsing deeply nested whens.

* Drop unused smallvector
* No need to copy xmrPathSuffix, simplify

Fixes #5003.

This commit parallelizes hash calculation. This reduces Dedup execution time by 40% in a large d...

closes #5554

This fixes a bug that `andr(pad(x:sint, n))` is canonicalized into `0`.

This appears to be a non-functional change.

* fixed ordering bug

* documentation

* addressed comments

---------

Co-authored-by: ...

This adds a folder for clock gates which removes clock gates that are transitively enable'd by o...

Also renames the data output field of the op to avoid aliasing with the built-in `getResultTypes...

Fixes #5531.
TLDR: `narrowOperationWidth()` copies attributes to a `comb.concat` operation, whi...

... based on a name-to-index `DenseMap` built from the `hw::ModulePortInfo` struct.
Needed in v...

Unclear what this models/means, and instead of doubling down
on workarounds lets drop this unti...

closes #5524

Async reset annotations are currently gathered sequentially. We can instead parallelize the accu...

This commit deprecates addMuxPragma flag in LowerToHW and implements lowering of MuxCell intrins...

Fix a compile error in nightly tests

Also changes to that the `clock-gate-regs` options actually implements clock gates instead of a ...

This adds `anonymousType` to type storages of bundle/vector/enum/alias type and define `getAnony...

* Split out DenseMapInfo specialization: https://reviews.llvm.org/D150997

Long delayed, this should fix #5488. It also removes the shorthand syntax.

Co-authored-by: Pai Li <[email protected]>
Co-authored-by: Caleb <[email protected]>

Change the FIRRTL emitter to use v3.0.0 of the FIRRTL specification.
Logic for emitting an older...

Move FIRRTL Version code into a header to enable reuse of this in other
places (in the future).
...

In the preprocess there seems to be an unintended use of `walk`. Currently we walk the entire c...

Particularly, clarify can't force a single element of an aggregate.

In large designs, it takes non-negligible amount of time to construct instance graphs (especiall...

Greatly reduces the number of ops in real designs

wc -l foo.mlir foo5.mlir
2247057 foo.ml...

As pointed out in https://github.com/llvm/circt/pull/5512, if there was an unreachable module fr...

This PR implements FIRRTLTypeSwitch which extends TypeSwitch so that we can use firrtl::type_{ca...

This changes LowerFIRRTLToHW to use backedges instead of temporary wire
operations. The tempora...

This adds a test to show the behaviour when a dead module instantiates a
child module, and uses...

When we lower input ports on instances, if there are zero or multiple
writers to the input port...

This change removes some cached information related to how module ports
relate to instance resu...

Enforce general requirement that all elements of something
implementing FieldIDTypeInterface mu...

Avoid constructing a null Location.

AFAIK presently unreachable.

These cases shouldn't be reachable, tweak handling.

This adds SV attributes support for comb mux op. Mux canonicalization is disabled if there is SV...

Previously, this would have emitted as `always @(edge clock or edge en)` which is invalid verilo...

This commit parallelizes the post processing of InferWidth. InferenceTypeUpdate just updates all...

Update the FIRRTL exporter to properly escape literal identifiers.

Signed-off-by: Schuyler Eldr...

Cleanup the `HWExportModuleHierarchyPass` pass in the following ways:

1. Do not emit JSON dir...

Use symbols to emit memory metadata. This is required to ensure that the
instance names in the...

Pass 2-state flag on construction of elementwise logical op.

Assuming lowerElementwiseLogical...

Adapted solver constraints to ensure all outputs must be equal.

Add two new property-aggregate types: `firrtl.list` and `firrtl.map`.

lementType -> elementType.

NFC since we don't generate accessors (for friendlier const access...

* Add Windows (firtool.exe)
* Remove Ubuntu 18.04 (runner is deprecated)
* Name archives based...

As mentioned in the removed TODO, `AllocateState` currently has an expensive combination of `mov...

for some reason, this also exposed a missing include in `circt-reduce.cpp`.

This finished support for handling InstanceOps with properties by
converting them into ObjectOp...

Was causing problems in build since SV passes wasn't a dep.

Change HWExportModuleHierarchy to use the optional "hw.verilogName" of an
instance as opposed to...

Add the `LowerFirMem` pass which lowers `seq.firmem` ops to a
corresponding `hw.module.generate...

Flows using this parameter will need to be updated.

Separated from #5167. This commit implements parser changes to support type alias.

Currently...

This commit adds an explicit 'go' signal to the pipeline abstraction.
This signal is used to in...

... for those times when you don't want to externalize a clock gate. My immediate use for this i...

* [FIRRTL] Reset values added in InferResets are now const.

This will facilitate future work ...

Signed-off-by: Schuyler Eldridge <[email protected]>

Add a utility to get the element name attribute from a bundle type.
Previously, this was only av...

Cleanup trailing whitespace in a test.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifi...

Change the MLIR printing/parsing of the MLIR representation of FIRRTL
bundle types to use quoted...

Factor common code for MLIR parsing of bundle field names into a common
static function.

Signed...

Fix #5459. Use namehints and name attributes on module boundary as port names of extracted modul...

Fix #5465. This fixes an issue that constants used by both designs and testcode.

The canonicalizer no longer accesses the op after it has been erased.

Optionally keep both info and fir locations during parsing,
and emit all (other) FileLineCol lo...

This implements `type_isa/type_cast/type_dyn_cast/type_dyn_cast_or_null`.
When a given type is ...

Add a new `FirMemOp` to the Seq dialect to capture the semantics of
FIRRTL memories at the HW l...