Bring into line with language terms.

Used to express RWProbe's using inner symbols to point at the target.

Add missing source locators for modules (module, extmodule, and intmodule)
and their ports.

Sig...

Change the FIRRTL emitter to use the "neverbreak" pretty printer token
before comments. This pr...

Fixes #5664

- Add and/or reduce for BitsSignal
- Add and reduce for ArraySignal
- Import Reset to pycde

Fixed test

Update the FIRRTL emitter to support optional group declarations and
definitions. This causes t...

Add parsing of optional groups, both declarations and definitions. These
will be rejected if th...

Move the sub-statement parsing lambda into a proper function. This is
done in preparation to en...

These are not presently handled (or generated), but
be good and report if they're encountered.

The previous approach worked for ref-only-agg interiors
that weren't under the root, but would ...

Found by tidy:

error: unmatched 'NOLINTEND' comment without a previous 'NOLINTBEGIN' comment [c...

(tidy's readability-inconsistent-declaration-parameter-name)

Lowers to a fairly standard fifo implementation. Will add more target-optimized implementations ...

Some cleanup of ESI .td files to make it possible to reference ESI from other dialects

* Adds i...

This reverts commit 919e7d30e452aafe8e2197bdd2b3c086282a1b2d.

Broke the PyCDE tests with: `Type...

Fixed: #5653

Bugfix. Any design which had an external module would cause this pass to
crash.

Introduces ops for the basic Ibis structural constructs.

Signed-off-by: Schuyler Eldridge <[email protected]>

The 'getPortNameAttr' functionality is generic. Move it into a new
support header and rename it.

Add support for lowering when statements which exist in group definitions.

Signed-off-by: Sch...

Split from #4502.

Add intrinsic modules to the FIRRTL emitter.

Signed-off-by: Schuyler Eldridge <schuyler.eldridg...

Move logic for emitting external module parameters into a function. This
is done as prerequisit...

Change the MLIR assembly format for `firrtl.groupdecl` to avoid reliance
on an attribute diction...

Change an incorrect usage of "unsigned long" in a definition to match the
"size_t" in the accomp...

Add operations to represent FIRRTL optional groups.

Signed-off-by: Schuyler Eldridge <schuyler....

These cannot be strictconnect'd.

Fixes #5650.

This fixes a bug that type_cast doesn't work well if a request type is `TypeInterface`.

Add statistics to track the total number of arcs and the total number of operations deduped in t...

We really need that trailing whitespace cleanup job...

Signed-off-by: Schuyler Eldridge <schuyl...

Fix trailing whitespace in a test. (We really need to just clean this up
automatically...)

Sig...

Combine the variants and allow specifying target as InnerSymTarget.

Add convenience wrappers ...

Partition inner symbols to the lowered fields by index, error if any symbols
target fieldID's n...

Not creating symbols, unnecessary work.

Add a LowerFirMems pass to the Arcilator pipeline so that FirMems end up in a format Arcilator c...

This commit manually declares user defined type storages.

#5577, #5575

Re. the lowering; `verif.print` lowers directly to a `sv.fwrite` via. inspection...

This commit reduces the execution time of InferResets by 30%~40%. Since it's costly to walk the ...

This change splits the python wheel upload into 2 stages (separate jobs). In the
first stage, w...

Do not try to resolve use-before-def on LTL expressions by spilling them
to a wire. LTL express...

* added repeat op

* cleaner documentation

* some formatting stuff

* add another newline...

Reflected in HW lowering, and used by e.g. the register materialization pass to carry register n...

This PR mechanically replaces type casts with `firrtl::type*` casts which strips outer most type...

Signed-off-by: Schuyler Eldridge <[email protected]>

While they can be useful sometimes, as step towards making these
opaque handles instead of stri...

ModuleNamespace is used for tracking used and generating new
`inner_sym`s. This code is mistak...

Drop the HWInnerRefAttr wrapper, use InnerRefAttr directly.

Bit of source code archaeology su...

Fixes pypi wheel upload condition for nightly runs. See #5431.

We will be porting an internal language over to CIRCT. This dialect will
be the entry point int...

An external class is to a class what an external module is to a
module. It captures just the ty...

* add invoke operation

* add invoke emitter

* add endline.

* update error message.

*...

This PR adds `getAsKey` methods to type storages. Close https://github.com/llvm/circt/issues/5568

This codepath assumes when the input attribute is not an Attribute, it
has a value member. This...

Fixes #5490.

Don't break apart in/out requests. Create an op interface to avoid having to rea...

This adds interfaces around the existing ClassOp and ClassFieldOp. The
interfaces are just abst...

There's currently no C++ API to build a ListAttr. The default builder
is reasonable--it takes an...

Fixes #5592.

Current behavior is to silently use the first we happen to discover.

Reachable by putting OMI...

Nearly NFC -- while visiting also drop code for special handling
of signal driving annotations ...

Here's a stab at the `hw.triggered` operation.
I think the main issue is to decide where to pla...

Code not under test.

Closes #5576.

Moving this since in the (near) future the verif dialect and HW module paramete...

Switch the depth parameter of `FirMemType` from 32 to 64 bits, since the
upstream FIRRTL operati...

* Fix ordering of operands in ScheduledPipelineOp::build

* clang format

* Remove newlines ...

Currently the `LowerFirMem` pass inserts `HWModuleGeneratedOp`s all the
way at the top of the f...

* bug fixes

* rewrite test case

* added newline

* documentation comment

Import https://github.com/llvm/llvm-project/commit/d138c8914822a3e2c3277ba30caf2215632134b6.
T...

Will emit `CompRegOp` instead of `CompRegClockEnabledOp`s for pipelines without stall signals.
...

Remove trailing whitespace in a test.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifiv...

Add the `--dedup` flag to arcilator to control arc deduplication.

Modify the behavior of the firtool/lower-to-hw flag "emit-asserts-as-svas"
and "emit-chisel-ass...

Squelch warning, and LLVM-style-ify dump method.
(sometimes elided, always marked noinline, som...

Adds a pass which analyses the module hierarchy to eliminate `inout` ports in favor of:
1. poki...