ObjectOp is a declaration of an object in firrtl, which in turn is an instance
of a class. Obje...

Don't leave handler attached, and ensure lifetime of the lambda
capture re:errorCount variable ...

Accept operations from the Verif and LTL dialects in firtool, and call
the Verif-to-SV lowering ...

Factor out `getConstantInt`, `isConstantZero`, and `isConstantOne` from
the Seq dialect folders ...

Add the `custom<KeywordBool>` parser/printer directive that allows for
booleans to be parsed and...

This implements LinkModulesPass that is a core logic of `om-linker`.
The input IR consists of m...

Since EmitOMIR is a firrtl::CircuitOp pass, don't attempt to access or modify
or insert into th...

Fix PyCDE after #5703.

This change moves from using plain StringAttrs and SymbolOpInterface to
InnerSymAttr and InnerS...

Using the HWTestModuleOP for testing, ExportVerilog is updated to use the port order in the modu...

Separate PortList from HWModuleLike and force users to actually define the interface if they dec...

Fixes #5011.

This implements a parser for a new module style. This module style uses ModuleType to store it'...

Keywords cannot be used for type alias name. Reject them during parsing.
In practice, only buil...

This implements a canonicalizer `or(mux(c_1, a, 0), mux(c_2, a, 0), ..., mux(c_n, a, 0)) -> mux(...

Module Printing is getting long. Factor out specific parts of it in anticipation of implementa...

ExportVerilog has some long functions. Factor out parameter printing. This will make transitio...

* Add codeowners for Calyx

* Add mike to HW and Loopschedule

* move mort

Let AnalysisManager provide cached copy if available,
and be open to it being preserved across ...

Until standardize on a dedicated type, fix this.

(cherry picked from commit f93871fbbff2b4c4ac871e417354eeb09bd64ed6)

Continue to handle everything else in a single walk.

Walking the ref dataflow directly would ...

Leave internal (C++) name alone for now,
may want to call it something other than IntegerType
...

This should be added to an interface shared elsewhere,
(and with different signature suitable t...

Fixes test on NixOS.

This allows the generated Python bindings to generate a useful
constructor, which is impossible...

Add two new pseudo-reduction patterns:

- module-name-sanitizer
- module-internal-name-sanit...

Move the SymbolCache struct used by the FIRRTL circt-reduce library into
its own "detail" namesp...

Allow the FIRRTLOperandForwarder to work on operations with one operand.
This enables some clea...

Fix by-value Twine usage introduced in 9d9697344. Switch to constant
reference Twine (which is ...

Fixes #5722

Co-authored-by: Schuyler Eldridge <[email protected]>

These binding are very shallow and only support the use case of a single
InnerSymProperties wit...

cc https://github.com/llvm/llvm-project/issues/63276

Fixes #4004.

Touchup var exp regex.

Much needed cast operations to/from ESI.
Given that `dc.value`s have unnamed fields (which i th...

Add basic tests.

Promote the mostly-unused `modNameSpace` to the more narrow
`ModuleNamespac...

Added here: 53b1c077d661af3409786db8363ddf3656137937 .

Improve the names of generated registers inside HWMemSimImpl. Change from
a generic "_GEN" to ...

- accepting multiple types is data semantics encroaching the control-only land of DC.

These values aren't used anymore.

Add the DropNames pass to circt-reduce with the option to drop all names.
This has the benefit ...

In the FIRParser, the parseModule function is responsible for parsing all kinds
of modules (int...

Twine is dangerous to pass by value, and it is usualy not worth it to try. This
change passes it...

When passed a port index referring to a result port, this function would walk
off the end of the...

Test introduced by b1882258c45a7b903ba89714f5813d3c38e774d6 was broken.

Fix clang-tidy errors related to snake_case variable naming in the
HWMemSimImpl pass.

Signed-of...

Fix an inconsistency between the handling of read ports and read-write
ports when running HWMemS...

Lowering the Ibis control flow starts with converting all calls to the DC dialect's values with ...

A class is both a type of property-object, and a constructor function. Classes
are FModuleLike,...

Lower `firrtl.alias` to `hw.typealias`.
Create a global `hw.type_scope` and add the `hw.typede...

Co-authored-by: Nandor Licker <[email protected]>

A number of ArrayAttr inherent attributes in the FIRRTL dialect have custom
accessors defined, b...

This class is a temporary measure to ensure that hardware declarations do not
appear underneath ...

Fix a bug where an assertion could fire in ExportVerilog due incomplete
wire creation in Prepare...

Plumb a LoweringOptions const reference to more functions. This is done
in preparation for a fu...

Move a static function so that this can be used by an ealier static
function in a later commit. ...

`isa<.*Type>` in LowerTypes seems to be not updated. This fixes LowerTypes to use type alias awa...

This commit is based on firld work by Will. This commit adds a boilerplate and
minimal implemen...

Apply the same fix from: https://reviews.llvm.org/D154469

* scfToCalyx changes

* calyx-lowering-utils changes

* added dumb file to help test

* cl...

* use llvm::size() which wraps std::distance but is only enabled
if it'll be O(1).
* static ca...

Additionally, lower to ifdef synthesis, since there is no way to generate that from chisel.

T...

Resolves build issue in #5634.

It's illegal to modify port types within FModuleLike pass so change DropConst pass to a circuit ...

Close https://github.com/llvm/circt/issues/5665. This commit fixes a bug that
bound instances a...