Summary:
This adds `preds` comment lines to BB names for readability, while also
fixes some of e...

Reviewers: tlively, sbc100

Subscribers: dschuff, jgravelle-google, sunfish, llvm-commits

Tags:...

Summary:
After r355981, intrinsic arguments that are immediate values should be
marked as `ImmAr...

Summary:
Adds patterns to lower all the remaining setcc modes: lt, gt,
le, and ge. Fixes PR40912...

This reverts commit 106f0cdefb02afc3064268dc7a71419b409ed2f3.

This change impacts the AMDGPU sm...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356422 91177308-0d34-0410-b5e6-96231b3b...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356420 91177308-0d34-0410-b5e6-96231b3b...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356419 91177308-0d34-0410-b5e6-96231b3b...

Add support for min/max flavor selects in computeConstantRange(),
which allows us to fold compar...

Baseline tests for D59471 (InstCombine of `add nuw` and `uaddo` with
constants).

Patch by Dan R...

We need to allow [128,255] in addition to [-128, 127] to match gas.

git-svn-id: https://llvm.or...

Forgot to add a change to relax some asserts in r356396.

git-svn-id: https://llvm.org/svn/llvm-...

The default implementation does we want and is going to more compatible
with dynamic linking (-f...

This is preparation for D59506. The InstructionSimplify abs handling
is moved into computeConsta...

These are baseline tests for D59506.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@3...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356407 91177308-0d34-0410-b5e6-96231b3b...

For the i8, i16, and i32 instructions we were using a relocImm. Presumably we should for i64 as ...

Subscribers: arsenm, kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, hiraditya...

This change makes linking into .build-id atomic and safe to use.
Some users under particular wor...

- Do not use unnamed values in saddo tests
- Add tests for canonicalization of a constant arg0

...

The original change back in rL29307 explained this but it was
lost somewhere along the way.

Dif...

Differential Revision: https://reviews.llvm.org/D59505

git-svn-id: https://llvm.org/svn/llvm-pr...

Allow the clamp modifier on vop3 int arithmetic instructions in assembly
and disassembly.

This ...

This commit allows v_cndmask_b32_e64 with abs, neg source
modifiers on src0, src1 to be assemble...

After review comments, it was preferred to not teach MachineIRBuilder about
non-generic instruct...

Before, empty debug streams were written as 8 bytes (4 bytes signature + 4 bytes for the GlobalR...

This fixes a couple of unflushed raw_string_ostream bugs in recent
commits that only show up on ...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356393 91177308-0d34-0410-b5e6-96231b3b...

This reinstates r347934, along with a tweak to address a problem with
PHI node ordering that tha...

It uses the generic AArch64_IMM::expandMOVImm to get the correct
number of instruction used in i...

This patch follows some ideas from r352866 to optimize the floating
point materialization even f...

This allows better code size for aarch64 floating point materialization
in a future patch.

Revi...

It splits the login of actual instruction emission away from the logic
that figures out the appr...

Similar to previous change done for VPCOM and VPCMP

Differential Revision: https://reviews.llvm...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356383 91177308-0d34-0410-b5e6-96231b3b...

Delete temporarily constructed node uses for analysis after it's use,
holding onto original inpu...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356381 91177308-0d34-0410-b5e6-96231b3b...

Add an experimental buffer fat pointer address space that is currently
unhandled in the backend....

Follow-up to:
rL356338
rL356369

We can calculate an arbitrary vector constant minus the bitwidt...

This fixes the https://bugs.llvm.org/show_bug.cgi?id=40980.

Previously if string optimization o...

Follow-up to:
rL356338

Rotates are a special case of funnel shift where the 2 input operands
ar...

Pre-commit for D59363 (Add icmp UNDEF handling to SelectionDAG::FoldSetCC)

Approved by @uweigan...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356367 91177308-0d34-0410-b5e6-96231b3b...

Results in much nicer -help output:
```
$ ./bin/llvm-exegesis -help
USAGE: llvm-exegesis [option...

Summary:
Look past bitcasts when looking for parameter debug values that are
described by frame-...

Fixes https://bugs.llvm.org/show_bug.cgi?id=35094

The Dead register definition pass should leav...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356359 91177308-0d34-0410-b5e6-96231b3b...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356358 91177308-0d34-0410-b5e6-96231b3...

These were added in r355423.

We only use the autogenerated table to assist with the maintenance...

These are used to help convert OR->LEA when needed to avoid avoid a copy. They
aren't need after...

All the other instructions are printed with a preceeding tab.

git-svn-id: https://llvm.org/svn/...

The LangRef claimed this was required to be a constant, but this
appears to be wrong.

Fixes bug...

The only thing the print methods currently need to know is the string to print for the memory si...

AMDGPU would like to use these MVTs.

Differential Revision: https://reviews.llvm.org/D58901

Ch...

AMDGPU would like to have MVTs for v3i32, v3f32, v5i32, v5f32. This
commit does not add them, bu...

Fix up rL356335 by checking that CPSR is not read between
the compare and the branch.

git-svn-...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356348 91177308-0d34-0410-b5e6-96231b3b...

There are a few different issues, mostly stemming from using
generation based checks for anythin...

Following the suggestion in D59475.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35...

This is the same change as rL356290, but for signed add. It replaces
the existing ripple logic w...

Similar to the previous patch for VPCOM.

Differential Revision: https://reviews.llvm.org/D59398...

Previously we had a regular form of the instruction used when the immediate was 0-7. And _alt fo...

AMDGPU would like to have MVTs for v3i32, v3f32, v5i32, v5f32. This
commit does not add them, bu...

I am about to introduce some non-power-of-2 width vector MVTs. This
commit fixes a power-of-2 as...

Prep work for D51589

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356340 91177308-0...

Following the suggestion in D59450, I'm moving the code for constructing
a ConstantRange from Kn...

This was noted as a backend problem:
https://bugs.llvm.org/show_bug.cgi?id=41057
...and subseque...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356337 91177308-0d34-0410-b5e6-96231b3b...

The constant island pass currently only looks at the instruction immediately
before a branch for...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356335 91177308-0d34-0410-b5e6-96231b3...

Fold (x & ~y) | y and it's four commuted variants to x | y. This pattern
can in particular appea...

This is a subset of what was proposed in:
D59006
...and may overlap with test changes from:
D591...

Contains common logic to match a string to a register name.

git-svn-id: https://llvm.org/svn/l...

RISCVAsmParser::ParseRegister is called from AsmParser::parseRegisterOrNumber,
which in turn is ...

rL356292 reduces the size of scalar_to_vector if we know the upper bits are undef - which means ...

Two new kinds, BTF_KIND_VAR and BTF_KIND_DATASEC, are added.

BTF_KIND_VAR has the following spe...

Replaces existing i1-only fold.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356325...

Improved constant folding for PEXTRB/PEXTRW will be added in a future commit

git-svn-id: https:...

Summary:
In the new wasm EH proposal, `rethrow` takes an `except_ref` argument.
This change was ...

Summary:
Currently the order of these methods does not matter, but the following
CL needs to hav...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356314 91177308-0d34-0410-b5e6-96231b3b...

Summary:
Rewrite WebAssemblyFixIrreducibleControlFlow to a simpler and cleaner
design, which dir...

This follows the C++17 std::vector change and can simplify immediate
back() calls.

git-svn-id: ...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356309 91177308-0d34-0410-b5e6-96231b3b...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356306 91177308-0d34-0410-b5e6-96231b3b...

TimePassesHandler object (implementation of time-passes for new pass manager)
gains ability to r...

This relaxes some asserts about sizes, and adds an optional subreg parameter
to buildCopy().

Al...

tMOVr and tPUSH/tPOP/tPOP_RET have register constraints which can't be
expressed in TableGen, so...

Summary:
As noted by @andreadb in https://reviews.llvm.org/D59035#inline-525780

If we have `sex...

Summary:
@mclow.lists brought up this issue up in IRC, it came up during
implementation of libc+...

Switch BIC immediate creation for vector ANDs from custom lowering
to a DAG combine, which gives...

Summary:
At the exit of the loop, the compiler uses a register to remember and accumulate
the nu...

Summary:
This wasn't actually printing out a CMake warning, it was prepending
"WARN" to the mess...

The asm parser generates the immediate without the SAE bit. So for consistency we should generat...

A change of two parts:
1) A generic enhancement for all callers of SDVE to exploit the fact that...

Reduce the size of an any-extended i64 scalar_to_vector source to i32 - the any_extend nodes are...

Use the methods introduced in rL356276 to implement the
computeOverflowForUnsigned(Add|Sub) func...