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github.com/swiftwasm/swift-llvm

This repository is no longer in use, please refer to the LLVM monorepo https://github.com/swiftwasm/llvm-project
https://github.com/swiftwasm/swift-llvm

Teach getSCEVAtScope how to handle loop phis w/invariant operands in loops w/taken backedges

This patch really contains two pieces:
Teach SCEV how to fold a phi in the header of a loop ...

10c34d1b8ddc5591d95ac4b170b04ad77c2a3d6c authored over 5 years ago by Philip Reames <[email protected]>
Add convenience utility for replacing a range within a container with a

different range, in preparation for use in Clang.

git-svn-id: https://llvm.org/svn/llvm-project/...

b31d1763674f4464952feafc04b22f81dd372fa6 authored over 5 years ago by Richard Smith <[email protected]>
[globalisel] Fix iterator invalidation in the extload combines

Summary:
Change the way we deal with iterator invalidation in the extload combines as it
was sti...

bb2252a33d738ba305a3bd0d11692bb4c483ec37 authored over 5 years ago by Daniel Sanders <[email protected]>
[AMDGPU] Propagate function attributes thru bitcasts

AMDGPUPropagateAttributes will not work on function bitcatsts,
so move AMDGPUFixFunctionBitcasts...

dc6cf0fe9d21503eee744bf754ce8938a8b79b34 authored over 5 years ago by Stanislav Mekhanoshin <[email protected]>
Fix a bug w/inbounds invalidation in LFTR (recommit)

Recommit r363289 with a bug fix for crash identified in pr42279. Issue was that a loop exit tes...

d773cb7e1cd21435f0b7d380b0d0d57f59bf1f02 authored over 5 years ago by Philip Reames <[email protected]>
gn build: Merge r363483.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363610 91177308-0d34-0410-b5e6-96231b3b...

e6bda13f369a91a0e785f4231c3a2b03ab9762bc authored over 5 years ago by Peter Collingbourne <[email protected]>
gn build: Merge r363584.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363609 91177308-0d34-0410-b5e6-96231b3b...

d07c0627e3cecca93db3e36260365f87cda1a7fc authored over 5 years ago by Peter Collingbourne <[email protected]>
AMDGPU/GFX10: Don't generate s_code_end padding in the asm-printer

Summary:
The purpose of the padding is to guard against stale code being
fetched into the instru...

3c07918c35182735ba39fd1ee76359eb325dcbf4 authored over 5 years ago by Nicolai Haehnle <[email protected]>
Reduced test case for pr42279 in advance of the relevant re-commit + fix

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363601 91177308-0d34-0410-b5e6-96231b...

185d55ed9f67126c37290f32bd94c03df69f0e05 authored over 5 years ago by Philip Reames <[email protected]>
AMDGPU: Explicitly define a triple for some tests

Summary:
This is related to the changes to the groupstaticsize intrinsic in
D61494 which would o...

17d3a9f1c160e8a8617a1948c42b9999bd223d03 authored over 5 years ago by Nicolai Haehnle <[email protected]>
[EarlyCSE] Fix hashing of self-compares

Summary:
Update compare normalization in SimpleValue hashing to break ties (when
the same value ...

12c73face909e5fcbfe4fbb2785efa01bba865a3 authored over 5 years ago by Joseph Tremoulet <[email protected]>
[MemorySSA] Don't use template when the clone is a simplified instruction.

Summary:
LoopRotate doesn't create a faithful clone of an instruction, it may
simplify it before...

6327268c4cec24f485748a73326cf745ebba5967 authored over 5 years ago by Alina Sbirlea <[email protected]>
[GlobalISel][AArch64] Fold G_SUB into G_ICMP when it's safe to do so

Basically porting over the behaviour in AArch64ISelLowering to GISel. See
emitComparison for ref...

798f83b658242bef7b96d75368e987649bd39eb4 authored over 5 years ago by Jessica Paquette <[email protected]>
[X86] Add TB_NO_REVERSE to some memory folding table entries where the register form requires 64-bit mode, but the memory form does not.

We don't know if its safe to unfold if we're in 32-bit mode.

This is simlar to what was done to...

6750ca7ad7952dfce15082339c98d7ec8df0f85c authored over 5 years ago by Craig Topper <[email protected]>
LiveInterval.h: add LiveRange::findIndexesLiveAt function - return a list of SlotIndexes the LiveRange live at.

Differential revision: https://reviews.llvm.org/D62411

git-svn-id: https://llvm.org/svn/llvm-pr...

97e04d1cf3037b97457707f05203c27d71fcb93c authored over 5 years ago by Valery Pykhtin <[email protected]>
[X86][SSE] Scalarize under-aligned XMM vector nt-stores (PR42026)

If a XMM non-temporal store has less than natural alignment, scalarize the vector - with SSE4A w...

22af01a41402861dd1eaf9a2210a247b7c5a7f65 authored over 5 years ago by Simon Pilgrim <[email protected]>
AMDGPU: Make getreg intrinsic inaccessiblememonly

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363591 91177308-0d34-0410-b5e6-96231b3b...

fcf015b682f0e6dcf5e2f3c213b0f5d3ddae2856 authored over 5 years ago by Matt Arsenault <[email protected]>
[MemorySSA] Add all MemoryPhis before filling their values.

Summary:
Add all MemoryPhis in IDF before filling in their incomign values.
Otherwise, a new Phi...

e0ff6cd9635ae76729824cd8870addba56f18e30 authored over 5 years ago by Alina Sbirlea <[email protected]>
[FastISel] Skip creating unnecessary vregs for arguments

This behavior was added in r130928 for both FastISel and SD, and then
disabled in r131156 for Fa...

d3cf21a26759271fa81fa9bd74ab4b3b5107a990 authored over 5 years ago by Francis Visoiu Mistrih <[email protected]>
[AMDGPU] gfx1010 wavefrontsize intrinsic folding

Differential Revision: https://reviews.llvm.org/D63206

git-svn-id: https://llvm.org/svn/llvm-pr...

95dd0d84d21ea397636287892bf0df588711566a authored over 5 years ago by Stanislav Mekhanoshin <[email protected]>
AMDGPU: Fold readlane/readfirstlane calls

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363587 91177308-0d34-0410-b5e6-96231b3b...

55ce7b4ea98ce61e1d4371bf0e42d3ae3890c967 authored over 5 years ago by Matt Arsenault <[email protected]>
[AMDGPU] Pass to propagate ABI attributes from kernels to the functions

The pass works in two modes:

Mode 1: Just set attributes starting from kernels. This can work a...

f1a5ef5a39d61698f7da9c4f592d5ea1803624a2 authored over 5 years ago by Stanislav Mekhanoshin <[email protected]>
gn build: Merge r363541

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363583 91177308-0d34-0410-b5e6-96231b3b...

c0de78b22080e541a867162203de479367f54219 authored over 5 years ago by Nico Weber <[email protected]>
[X86][AVX] Split under-aligned vector nt-stores.

If a YMM/ZMM non-temporal store has less than natural alignment, split the vector - either they ...

1d6c2fbdd1f8dfe6534b81df84755ee580bb50f7 authored over 5 years ago by Simon Pilgrim <[email protected]>
[LV] Suppress vectorization in some nontemporal cases

When considering a loop containing nontemporal stores or loads for
vectorization, suppress the v...

31868b92dfcc70b18adad342857b3de7bbace164 authored over 5 years ago by Warren Ristow <[email protected]>
GlobalISel: Ignore callsite attributes when picking intrinsic type

A target intrinsic may be defined as possibly reading memory, but the
call site may have additio...

bb2597ae2fdf411ddc394824416aa3323c14d17d authored over 5 years ago by Matt Arsenault <[email protected]>
GlobalISel: Verify intrinsics

I keep using the wrong instruction when manually writing tests. This
really needs to check the n...

6f81a49f5c4489724aa1115b69c043fa94436ffd authored over 5 years ago by Matt Arsenault <[email protected]>
AMDGPU/GlobalISel: Account for multiple defs when finding intrinsic ID

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363578 91177308-0d34-0410-b5e6-96231b3b...

33482eea4c6ddeaacbbd04b67159af6a1966321e authored over 5 years ago by Matt Arsenault <[email protected]>
[AMDGPU] gfx1010 wave32 metadata

Differential Revision: https://reviews.llvm.org/D63207

git-svn-id: https://llvm.org/svn/llvm-pr...

c33d0e66505b286414f9dfaf3348388fdaf6747c authored over 5 years ago by Stanislav Mekhanoshin <[email protected]>
AMDGPU/GlobalISel: Implement select for G_ICMP and G_SELECT

Reviewers: arsenm

Subscribers: kzhuravl, jvesely, wdng, nhaehnle, yaxunl, rovka, kristof.beyls,...

2d928b87dee907eb069a68e54105a1688d0733c4 authored over 5 years ago by Tom Stellard <[email protected]>
[Remarks] Extend -fsave-optimization-record to specify the format

Use -fsave-optimization-record=<format> to specify a different format
than the default, which is...

1cb383ef62173c35ee4c3ee7f5dde9739e8cc4de authored over 5 years ago by Francis Visoiu Mistrih <[email protected]>
[X86] combineLoad - begun making the load split code more generic. NFCI.

This is currently only used for ymm->xmm splitting but we shouldn't hardcode the offsets/alignme...

3ea8c2ac6a9772267d3ad442756cffca66c95f83 authored over 5 years ago by Simon Pilgrim <[email protected]>
PHINode: introduce setIncomingValueForBlock() function, and use it.

Summary:
There is PHINode::getBasicBlockIndex() and PHINode::setIncomingValue()
but no function ...

bdd7b78551807d737c1d8a7f0541e899d67bb95c authored over 5 years ago by Whitney Tsang <[email protected]>
[X86][SSE] Add tests for underaligned nt loads

Test both 'unaligned' (which we should just use regular unaligned loads) and 'subvector aligned'...

dbb1cec2e70078e863cd9c210da60dd22227ec53 authored over 5 years ago by Simon Pilgrim <[email protected]>
[X86][SSE] Prevent misaligned non-temporal vector load/store combines

For loads, pre-SSE41 we can't perform NT loads at all, and after that we can only perform vector...

bfe7eb96c9736b21e7790d493e39b19c514ed478 authored over 5 years ago by Simon Pilgrim <[email protected]>
InferAddressSpaces: Fix cloning original addrspacecast

If an addrspacecast needed to be inserted again, this was creating a
clone of the original cast ...

6b4d361457bf9103e1f2423c34347b1a3cdd8675 authored over 5 years ago by Matt Arsenault <[email protected]>
AMDGPU: Ignore subtarget for InferAddressSpaces

Even if the target doesn't have flat instructions, addrspace(0) is
still flat. It just happens t...

6f9792a23815e2f36b17263149dbe01484bb9d8e authored over 5 years ago by Matt Arsenault <[email protected]>
AMDGPU: Mark exp/exp.compr as inaccessiblememonly

Should also be marked writeonly, but I think that would require
splitting the version with done ...

14dc077c2042cdbaa26dcfaa12b1809ed1044d56 authored over 5 years ago by Matt Arsenault <[email protected]>
AMDGPU/GlobalISel: Fix default mapping for non-register operands

Tests will be in future commits when new intrinsics are handled here.

git-svn-id: https://llvm....

baa4b8244b7eb151d21b41d4f3c5ba78a0b17027 authored over 5 years ago by Matt Arsenault <[email protected]>
AMDGPU: Cleanup custom PseudoSourceValue definitions

Use separate enums for each kind, avoid repeating overloads, and add
missing classof implementat...

b6ebfc02b317c8dab03ea01d7f5e90669a384e03 authored over 5 years ago by Matt Arsenault <[email protected]>
[CodeGen] Check for HardwareLoop Latch ExitBlock

The HardwareLoops pass finds exit blocks with a scevable exit count.
If the target specifies to ...

5f13aa40626739698a88d18bf851a72064e6e7b8 authored over 5 years ago by Sam Parker <[email protected]>
[X86][SSE] Avoid unnecessary stack codegen in NT store codegen tests.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363552 91177308-0d34-0410-b5e6-96231b3b...

208eae0feb1d4b20b10f8226f885e603f5e23040 authored over 5 years ago by Simon Pilgrim <[email protected]>
AsmPrinter: add doc-string for EmitLinkage

Change-Id: I376fcbd58f84a2aac6aaf744bc1665c92d312b25

git-svn-id: https://llvm.org/svn/llvm-proj...

ce390642d524b587b0aefb6ffd0237d2e9bbbe5e authored over 5 years ago by Nicolai Haehnle <[email protected]>
gn build: Merge r363530

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363549 91177308-0d34-0410-b5e6-96231b3b...

f95bc3347d67efe3229ea677ee1f98994bf4adc0 authored over 5 years ago by Nico Weber <[email protected]>
[LV] Deny irregular types in interleavedAccessCanBeWidened

Summary:
Avoid that loop vectorizer creates loads/stores of vectors
with "irregular" types when ...

784000b4c2abfaf40f48d8a077611272bd729f7d authored over 5 years ago by Bjorn Pettersson <[email protected]>
Test forward references in IntrinsicEmitter on Neon LD(2|3|4)

This patch tests the forward-referencing added in D62995 by changing
some existing intrinsics to...

52598dbf5e8896f038520df52e3a9a800dee0091 authored over 5 years ago by Sander de Smalen <[email protected]>
[DAGCombiner] [CodeGenPrepare] More comprehensive GEP splitting

Some GEPs were not being split, presumably because that split would just be
undone by the DAGCo...

e36a3e35dd7a237c54955b068b6ca0252b485116 authored over 5 years ago by Luis Marques <[email protected]>
Fix clang -Wcovered-switch-default after stack-id change by D60137

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363543 91177308-0d34-0410-b5e6-96231b3b...

ba4b2d50e144b6cfbed01ccc25629c34b228db87 authored over 5 years ago by Fangrui Song <[email protected]>
[SelectionDAG] Fold insert_subvector(undef, extract_subvector(v, c), c) -> v in getNode

This is already done in DAGCombiner::visitINSERT_SUBVECTOR, but this helps a number of shuffles ...

ec69a27d0a634a618f01cf1d3edc509b73dc483b authored over 5 years ago by Simon Pilgrim <[email protected]>
[SCEV] Use NoWrapFlags when expanding a simple mul

Second functional change following on from rL362687. Pass the
NoWrapFlags from the MulExpr to In...

57a7d9d49d3e224d387849c540e4484f725e78db authored over 5 years ago by Sam Parker <[email protected]>
[llvm-objdump] Use %08 instead of %016 to print leading addresses for 32-bit binaries

Reviewed By: grimar

Differential Revision: https://reviews.llvm.org/D63398

git-svn-id: https:/...

400438c3c0fe0d233819a493ccc52d30bffd99cc authored over 5 years ago by Fangrui Song <[email protected]>
Propagating prior merge from 'llvm.org/master'.

9290bd1e343c5eb57bbf1c5b0420a83c401976f5 authored over 5 years ago by Automerger <Automerger@Swift>
[lit] Delete empty lines at the end of lit.local.cfg NFC

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363538 91177308-0d34-0410-b5e6-96231b3b...

1002960b9df562de440b30d307ac1c50602e5a1b authored over 5 years ago by Fangrui Song <[email protected]>
[NFC][Codegen] Standalone tests for icmp eq/ne (urem %x, C), 0 -> icmp eq/ne %x, 0 fold (D63390)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363537 91177308-0d34-0410-b5e6-96231b3b...

e3afbf5368f03be68c43ae7f05b4362f1b3da372 authored over 5 years ago by Roman Lebedev <[email protected]>
[ARM] Fix another -Wunused-variable in -DLLVM_ENABLE_ASSERTIONS=off builds after D63265

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363535 91177308-0d34-0410-b5e6-96231b3b...

992d474561f1299312510aa3db0ec1fb85516c78 authored over 5 years ago by Fangrui Song <[email protected]>
[ARM] Fix -Wunused-variable in -DLLVM_ENABLE_ASSERTIONS=off builds after D63265

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363534 91177308-0d34-0410-b5e6-96231b3b...

679d03e384e821fc52c5b0a13c94dd6e91bdc21f authored over 5 years ago by Fangrui Song <[email protected]>
Describe stack-id as an enum

This patch changes MIR stack-id from an integer to an enum,
and adds printing/parsing support fo...

f4bff34d4d8ad5565ef99568411577439e5da024 authored over 5 years ago by Sander de Smalen <[email protected]>
[ARM] Remove ARMComputeBlockSize

Forgot to remove file!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363532 9117730...

82ad3d12cc52409acae3930934ba1e8034c32cae authored over 5 years ago by Sam Parker <[email protected]>
[ARM] Add ARMBasicBlockInfo.cpp

Forgot to add file!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363531 91177308-0...

659a32042076a406b2957e95cc55f8740a189656 authored over 5 years ago by Sam Parker <[email protected]>
[ARM] Extract some code from ARMConstantIslandPass

Create the ARMBasicBlockUtils class for tracking and querying basic
blocks sizes so we can use t...

2d3fee0bf7a017b7fc5cb4b6fa2e260bbbd7ee4e authored over 5 years ago by Sam Parker <[email protected]>
Re-commit r357452 (take 3): "SimplifyCFG SinkCommonCodeFromPredecessors: Also sink function calls without used results (PR41259)"

Third time's the charm.

This was reverted in r363220 due to being suspected of an internal benc...

8daad51954f1be30f1c8b83618a6485d6f8f57af authored over 5 years ago by Hans Wennborg <[email protected]>
[SimplifyCFG] Fix prof branch_weights MD while removing unreachable switch cases

SimplifyCFG has a bug that results in inconsistent prof branch_weights metadata
if unreachable s...

90e12ffba71f4d3bd617a1ffacec209c2026292a authored over 5 years ago by Yevgeny Rouban <[email protected]>
PowerPC: Optimize SPE double parameter calling setup

Summary:
SPE passes doubles the same as soft-float, in register pairs as i32
types. This is all...

05b9698f31b026b7d17b4c38c9b03e67c4ddfd0b authored over 5 years ago by Justin Hibbits <[email protected]>
[yaml2obj][MachO] Don't fill dummy data for virtual sections

Summary:
Currently, MachOWriter::writeSectionData writes dummy data (0xdeadbeef) to fill section...

f99a09c3b08d5727c9b217ecdee2b79c433fc580 authored over 5 years ago by Seiya Nuta <[email protected]>
[llvm-objcopy] Add elf32-sparc and elf32-sparcel target

Summary:
The "sparc"/"sparcel" architectures appears in ArchMap (used by -B option) but not in O...

fef0e8cd354dba6d476ff4f199dacdd5df8ee239 authored over 5 years ago by Seiya Nuta <[email protected]>
[X86] Add TB_NO_REVERSE to some folding table entries where the register from uses the REX prefix, but the memory form does not.

It would not be safe to unfold the memory form the register form
without checking that we are co...

b05cc79bff6a66ecc607607604b1b582d352ae45 authored over 5 years ago by Craig Topper <[email protected]>
[InstSimplify] Fix addo/subo undef folds (PR42209)

Fix folds of addo and subo with an undef operand to be:

`@llvm.{u,s}{add,sub}.with.overflow` al...

d09f140cd1ebdfcabc333c45fe7e7fe59752bdf9 authored over 5 years ago by Roman Lebedev <[email protected]>
[AsmPrinter] Make EmitLinkage and EmitVisibility public

Summary:
This allows target to implement custom emit of global variables if
required. See subseq...

e51018c2299b60912b7b4d1aaf6e83f1e905edb5 authored over 5 years ago by Nicolai Haehnle <[email protected]>
AMDGPU: Prepare for explicit absolute relocations in code generation

Summary:
We will use absolute relocations for LDS symbols.

Change-Id: I9a32795ed0ea835e433a7871...

6435d005d68411f87ef42bbda5c4d48f6edfa54b authored over 5 years ago by Nicolai Haehnle <[email protected]>
AMDGPU: Be explicit about whether the high-word in SI_PC_ADD_REL_OFFSET is 0

Summary:
Instead of encoding a high-word of 0 using a fake TargetGlobalAddress,
just use a liter...

58b383765e525fe10bca7c10d5dbc1ed1074947a authored over 5 years ago by Nicolai Haehnle <[email protected]>
AMDGPU/GFX10: Support DLC bit in llvm.amdgcn.s.buffer.load intrinsic

Summary: Change-Id: Ie4c971462a7749740938c687144e77441dac2539

Reviewers: rampitec, arsenm

Subs...

d116e8400b55d43623fd8350a69f7a1e42c7b8f6 authored over 5 years ago by Nicolai Haehnle <[email protected]>
[AMDGPU] gfx10 conditional registers handling

This is cpp source part of wave32 support, excluding overriden
getRegClass().

Differential Revi...

c6fce1250e5007a497fe3c0e53dbaa00d820e029 authored over 5 years ago by Stanislav Mekhanoshin <[email protected]>
[CodeGenPrepare][x86] shift both sides of a vector select when profitable

This is based on the example/discussion in PR37428:
https://bugs.llvm.org/show_bug.cgi?id=37428
...

d049b8952bfac483d76ddb1cb026aff2fa3a8760 authored over 5 years ago by Sanjay Patel <[email protected]>
[x86] split 256-bit vector selects if operands are vector concats

This is similar logic/motivation to the select splitting in D62969.

In D63233, the pattern chan...

78f1b314644d2968590e41c71d3eec2b853642f8 authored over 5 years ago by Sanjay Patel <[email protected]>
[X86] CombineShuffleWithExtract - handle cases with different vector extract sources

Insert the shorter vector source into an undef vector of the longer vector source's type.

git-s...

06e81472730158e50cbc9f660d5db486f8a57f61 authored over 5 years ago by Simon Pilgrim <[email protected]>
Propagating prior merge from 'llvm.org/master'.

a40651b56ee4c9dc56b2e8e09539efd889107fea authored over 5 years ago by Automerger <Automerger@Swift>
gn build: Merge r363444

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363505 91177308-0d34-0410-b5e6-96231b3b...

29fd1c2a34d2b420d22edfb2aaa48eb35e73dd03 authored over 5 years ago by Nico Weber <[email protected]>
[X86] CombineShuffleWithExtract - assert all src ops types are multiples of rootsize. NFCI.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363501 91177308-0d34-0410-b5e6-96231b3b...

0f6694464b8f52cf92b3d1edf953dd757ffffecc authored over 5 years ago by Simon Pilgrim <[email protected]>
[X86][AVX] Handle lane-crossing shuffle(extract_subvector(x,c1),extract_subvector(y,c2),m1) shuffles

Pull out the existing (non)lane-crossing fold into a helper lambda and use for lane-crossing una...

170bbaa5a54e2da4c02c47104921bad5ee64a4d1 authored over 5 years ago by Simon Pilgrim <[email protected]>
[X86][AVX] Decode constant bits from insert_subvector(c1, c2, c3)

This mostly happens due to SimplifyDemandedVectorElts reducing a vector to insert_subvector(unde...

2720bd6686713de365b97d8c19776552c50979f9 authored over 5 years ago by Simon Pilgrim <[email protected]>
[NFC][MCA][X86] Add one more 'clear super register' pattern - movss/movsd load clears high XMM bits

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363498 91177308-0d34-0410-b5e6-96231b3b...

dc0aa24fcdfe2123df70ecf03635351b7ee75d4e authored over 5 years ago by Roman Lebedev <[email protected]>
[NFC][MCA][X86] Add baseline test coverage for AMD Barcelona (aka K10, fam10h)

Looking into sched model for that CPU ...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/tr...

fb0a468b49cb537a507553e3e4221078b2351557 authored over 5 years ago by Roman Lebedev <[email protected]>
[Clang] Harmonize Split DWARF options with llc

Summary:
With Split DWARF the resulting object file (then called skeleton CU)
contains the file ...

42e2da74cf9b0df03019fb55a15309f1d2d8cac4 authored over 5 years ago by Aaron Puchert <[email protected]>
[PowerPC] Set the innermost hot loop to align 32 bytes

Summary:
If the nested loop is an innermost loop, prefer to a 32-byte alignment, so that
we can ...

f8a4e52cc95d9568c9730b8db24389b6dc3befaa authored over 5 years ago by Kang Zhang <[email protected]>
[clang] Add storage for APValue in ConstantExpr

Summary:
When using ConstantExpr we often need the result of the expression to be kept in the AS...

9e1cb6616dbcabac9d826a295a18fb82aa23e712 authored over 5 years ago by Gauthier Harnisch <[email protected]>
[BranchProbability] Delete a redundant overflow check

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363492 91177308-0d34-0410-b5e6-96231b3b...

dc69eb3bf3d11f065a9f4963f87a1120231c6533 authored over 5 years ago by Fangrui Song <[email protected]>
[SCEV] Use unsigned/signed intersection type in SCEV

Based on D59959, this switches SCEV to use unsigned/signed range
intersection based on the sign ...

b435405a043fbd11282be0bec93a42b1f1c54bf0 authored over 5 years ago by Nikita Popov <[email protected]>
Propagating prior merge from 'llvm.org/master'.

1717645743ef3a90c8899cbba19cf36638596beb authored over 5 years ago by Automerger <Automerger@Swift>
[SimplifyIndVar] Simplify non-overflowing saturating add/sub

If we can detect that saturating math that depends on an IV cannot
overflow, replace it with sim...

bf4a9f732581a6e85a904a7b3b612b658860ca7e authored over 5 years ago by Nikita Popov <[email protected]>
[RISCV] Regenerate remat.ll and atomic-rmw.ll after D43256

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363487 91177308-0d34-0410-b5e6-96231b3b...

5eaae6c4c2b4364378dc8a2be3ca8993514f4edf authored over 5 years ago by Fangrui Song <[email protected]>
[RISCV] Simplify RISCVAsmBackend::writeNopData(). NFC

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363486 91177308-0d34-0410-b5e6-96231b3b...

c5ac9abee742f9d8cda89294645726ae7c04fdc2 authored over 5 years ago by Fangrui Song <[email protected]>
[objcopy] Error when --preserve-dates is specified with standard streams

Summary: llvm-objcopy/strip now error when -p is specified when reading from stdin or writing to...

1f1f241e1685dddad2db4749a915f07cb1eaca26 authored over 5 years ago by Alex Brachet <[email protected]>
adding more fmf propagation for selects plus updated tests

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363484 91177308-0d34-0410-b5e6-96231b3b...

d71bd8db7b8c3f5e256f131cc83285ec1f0677ab authored over 5 years ago by Michael Berg <[email protected]>
Revert "adding more fmf propagation for selects plus tests"

This reverts rL363474. -debug-only=isel was added to some tests that
don't specify `REQUIRES: as...

118986bcda5457c564b09f0b8e103ef8a9adb29c authored over 5 years ago by Fangrui Song <[email protected]>
[InstCombine] Add tests to show missing fold opportunity for "icmp and shift" (nfc).

Summary:
For icmp pred (and (sh X, Y), C), 0

When C is signbit, expect to fold (X << Y) & sig...

34a27682ed02e6273e91b49bacf6bfc75e8da157 authored over 5 years ago by Huihui Zhang <[email protected]>
Reapply "GlobalISel: Avoid producing Illegal copies in RegBankSelect"

This reapplies r363410, avoiding null dereference if there is no
AltRegBank.

git-svn-id: https:...

daecbabf55cf11efe6edcd40df96ae7e9359ecf5 authored over 5 years ago by Matt Arsenault <[email protected]>
Add a map_range function for applying map_iterator to a range.

In preparation for use in Clang.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36347...

4000c17fc9b553dbe113251bb0ba2a68f6dc8ad7 authored over 5 years ago by Richard Smith <[email protected]>
Revert "GlobalISel: Avoid producing Illegal copies in RegBankSelect"

This patch breaks UBSan build bots. See
https://github.com/google/sanitizers/wiki/SanitizerBotRe...

49bf2d7b0f314922b1825e923ddc003f599566f4 authored over 5 years ago by Mitch Phillips <[email protected]>
adding more fmf propagation for selects plus tests

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363474 91177308-0d34-0410-b5e6-96231b3b...

aad9d5e5dd9bccf64421d544db81a8b55108667f authored over 5 years ago by Michael Berg <[email protected]>
[MBP] Move a latch block with conditional exit and multi predecessors to top of loop

Current findBestLoopTop can find and move one kind of block to top, a latch block has one succes...

7eae8125c63bb72c2103f17ba01d6eb1e7ca5052 authored over 5 years ago by Guozhi Wei <[email protected]>