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github.com/swiftwasm/swift-llvm

This repository is no longer in use, please refer to the LLVM monorepo https://github.com/swiftwasm/llvm-project
https://github.com/swiftwasm/swift-llvm

Fix r363773: Update Barcelona MCA tests.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363781 91177308-0d34-0410-b5e6-96231b3b...

96b71308194a7c3a485ffba531642c050ee85b82 authored over 5 years ago by Clement Courbet <[email protected]>
Propagating prior merge from 'llvm.org/master'.

a13b70864790bef7c5090447e061ec1a711847f5 authored over 5 years ago by Automerger <Automerger@Swift>
Make TargetParserTest.ARMExtensionFeatures not run out of memory on 32-bit (PR42316)

The test still probably shouldn't run this loop 17 million times, but at
least now it won't run ...

1e28f6ede44dfc4acc07634cd7ed17edbde917d6 authored over 5 years ago by Hans Wennborg <[email protected]>
[yaml2obj/obj2yaml] - Make RawContentSection::Info Optional<>

This allows to customize this field for "implicit" sections properly.

Differential revision: ht...

301f3b0628aec583bdf819f9bdce885da7af88e0 authored over 5 years ago by George Rimar <[email protected]>
[NFC][X86][MCA] Barcelona: add load/store/load-store-throughput tests

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363775 91177308-0d34-0410-b5e6-96231b3b...

1edcb734227704bc32ad25ecb3dc3a25d63e94f4 authored over 5 years ago by Roman Lebedev <[email protected]>
[NFC][X86][MCA] BdVer2: add load-store-throughput test

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363774 91177308-0d34-0410-b5e6-96231b3b...

84af9d904c839ededa7a4234e594d5761379cbe9 authored over 5 years ago by Roman Lebedev <[email protected]>
[X86] Add missing properties on llvm.x86.sse.{st,ld}mxcsr

Summary:
llvm.x86.sse.stmxcsr only writes to memory.
llvm.x86.sse.ldmxcsr only reads from memory...

cc47f49f3721ab76666ab82a97c05523bd227189 authored over 5 years ago by Clement Courbet <[email protected]>
[RISCV] Add lowering of global TLS addresses

This patch adds lowering for global TLS addresses for the TLS models of
InitialExec, GlobalDynam...

5fbcfbac5944159836e87ee394f371ce6b25e120 authored over 5 years ago by Lewis Revill <[email protected]>
vs integration: bump version nbr

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363769 91177308-0d34-0410-b5e6-96231b3b...

908043fbf18a3c0bb231d3ce281ca64eb253d466 authored over 5 years ago by Hans Wennborg <[email protected]>
Revert r359557 "vs integration: vs2019 support"

Turns out this worked on my machine because I still had VS2017 installed, but
it didn't actually...

eae6c24576a08ac01c0b4e69200f859429637312 authored over 5 years ago by Hans Wennborg <[email protected]>
Test commit access

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363763 91177308-0d34-0410-b5e6-96231b3b...

c40299a741f513b342118c4d03ffc5312eea5489 authored over 5 years ago by Yuanfang Chen <[email protected]>
[RISCV] Fix test after r363757

r363757 renamed ExpandISelPseudo to FinalizeISel, so the RUN line in
select-optimize-multiple.mi...

f74034c53d55a7db9434d198f7f313d477526a92 authored over 5 years ago by Alex Bradbury <[email protected]>
[NFC] move some hardware loop checking code to a common place for other using.

Differential Revision: https://reviews.llvm.org/D63478

git-svn-id: https://llvm.org/svn/llvm-p...

221779b03fe4dd00db84371e0ad64f8e7007702b authored over 5 years ago by Chen Zheng <[email protected]>
Rename ExpandISelPseudo->FinalizeISel, delay register reservation

This allows targets to make more decisions about reserved registers
after isel. For example, now...

5b56cc85b0ffae025723062f612739de6a75f522 authored over 5 years ago by Matt Arsenault <[email protected]>
[WebAssembly] Optimize ISel for SIMD Boolean reductions

Summary:
Converting the result *.{all,any}_true to a bool at the source level
generates LLVM IR ...

307315e0e9566fc96d47fcb35b42857988c48d0f authored over 5 years ago by Thomas Lively <[email protected]>
Re-commit r363744: [tblgen][disasm] Allow multiple encodings to disassemble to the same instruction

It seems macOS lets you have ArrayRef<const X> even though this is apparently
forbidden by the l...

10df6f5ff35bc3fc9c1706a8a30621026a766416 authored over 5 years ago by Daniel Sanders <[email protected]>
[demangle] Special case clang's creative mangling of __uuidof expressions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363752 91177308-0d34-0410-b5e6-96231b3b...

51e6c1d2249816d21eca8a3a520bab43d7e076ee authored over 5 years ago by Erik Pilkington <[email protected]>
[test] Change comment wording (NFC)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363751 91177308-0d34-0410-b5e6-96231b3b...

4c8927a330ef8b1d032190f99f1649a725ddf137 authored over 5 years ago by Evandro Menezes <[email protected]>
Revert [tblgen][disasm] Allow multiple encodings to disassemble to the same instruction

This reverts r363744 (git commit 9b2252123d1e79d2b3594097a9d9cc60072b83d9)

This breaks many bui...

90019298462854ac6301623cdfa99763911312b9 authored over 5 years ago by Jordan Rupprecht <[email protected]>
Print dylib load kind (weak, reexport, etc) in llvm-objdump -m -dylibs-used

Summary:
Historically llvm-objdump prints the path to a dylib as well as the
dylib's compatibili...

595bd8b12a69952d4a72cec617c4adfd2666ba29 authored over 5 years ago by Michael Trent <[email protected]>
[GlobalISel][Localizer] Remove redundant set lookup.

After changing the algorithm to only process the entry block we never revisit
a processed instru...

3c55ded6d1fd207ec54dd902cec57e3550ca365e authored over 5 years ago by Amara Emerson <[email protected]>
[tblgen][disasm] Allow multiple encodings to disassemble to the same instruction

Summary:
Add an AdditionalEncoding class which can be used to define additional encodings
for a ...

c46dd2b9d2fe9d51dc00b5f621ba9bf9c38d08f0 authored over 5 years ago by Daniel Sanders <[email protected]>
Recommit [SROA] Enhance SROA to handle `addrspacecast`ed allocas

[SROA] Enhance SROA to handle `addrspacecast`ed allocas

- Fix typo in original change
- Add add...

38735bb19599d9e7a0e8090106a33d31f8f6caf8 authored over 5 years ago by Michael Liao <[email protected]>
InstCombine: Pre-commit test for reassociating nuw

D39417

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363741 91177308-0d34-0410-b5e6-...

437ebb9c6e576f102866ee7b15f0d40f8f7106bd authored over 5 years ago by Matt Arsenault <[email protected]>
[ARM] Comply with rules on ARMv8-A thumb mode partial deprecation of IT.

Summary:
When identifing instructions that can be folded into a MOVCC instruction,
checking for ...

d8ca88c062f0d5a0c475570797513aec38ff2a82 authored over 5 years ago by Huihui Zhang <[email protected]>
[RISCV] Prevent re-ordering some adds after shifts

Summary:
DAGCombine will normally turn a `(shl (add x, c1), c2)` into `(add (shl x, c2), c1 << c...

7f53b8e34b6af8b2e647d25b3ef9aea0d0f77639 authored over 5 years ago by Sam Elliott <[email protected]>
[MachinePipeliner][NFC] Do resource tracking log only when requested.

In most cases we don't need to do resource tracking debug,
so leave them off by default.

git-sv...

cc384fa64694826cd63fec029a136a0aa3f6a59e authored over 5 years ago by Jinsong Ji <[email protected]>
[x86] add another test for load splitting with extracted stores (PR42305); NFC

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363732 91177308-0d34-0410-b5e6-96231b3b...

dddc90d3d6b46228b35c1dca57f75fa0873f504c authored over 5 years ago by Sanjay Patel <[email protected]>
Add debug location verification for !llvm.loop attachments.

This patch teaches the Verifier how to detect broken !llvm.loop
attachments as discussed in http...

d130a833d86c23b53dbd335219f434befa7ffe7e authored over 5 years ago by Adrian Prantl <[email protected]>
Fix broken debug info in in an !llvm.loop attachment in this testcase.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363730 91177308-0d34-0410-b5e6-96231b3b...

1d5e7014d2b9e7fa427e667b92f1c4169eb70937 authored over 5 years ago by Adrian Prantl <[email protected]>
[AMDGPU] gfx10 wave32 patterns

Differential Revision: https://reviews.llvm.org/D63511

git-svn-id: https://llvm.org/svn/llvm-pr...

d46e8d2b9984d9e87e05ccdad57cd0f55bce7547 authored over 5 years ago by Stanislav Mekhanoshin <[email protected]>
Revert Add debug location verification for !llvm.loop attachments.

This reverts r363725 (git commit 8ff822d61dacf5a9466755eedafd3eeb54abc00d)

git-svn-id: https://...

c22f7949797ef8dbeedb8c577edd5a6dd062e3ff authored over 5 years ago by Adrian Prantl <[email protected]>
[coroutines] Add missing pass dependency.

Summary:
CoroSplit depends on CallGraphWrapperPass, but it was not explicitly adding it as a pas...

04cfa1ef8da4a9122d2e739596d96c515fc3dbc9 authored over 5 years ago by Gor Nishanov <[email protected]>
Add debug location verification for !llvm.loop attachments.

This patch teaches the Verifier how to detect broken !llvm.loop
attachments as discussed in http...

ba29b473c9ebd4aa03da75f7a4f9b9a4e0a5c173 authored over 5 years ago by Adrian Prantl <[email protected]>
[PDB] Ignore .debug$S subsections with high bit set

Some versions of the Visual C++ 2015 runtime have line tables with the
subsection kind of 0x8000...

ddf63a4a7f536f3ca2186646c4550b59b065898b authored over 5 years ago by Reid Kleckner <[email protected]>
[AMDGPU] gfx1010 disassembler changes for wave32

Differential Revision: https://reviews.llvm.org/D63506

git-svn-id: https://llvm.org/svn/llvm-pr...

595bc8080704f24a00891484aaa87e0286da0d4d authored over 5 years ago by Stanislav Mekhanoshin <[email protected]>
[X86] Remove unnecessary line that makes v4f32 FP_ROUND Legal. NFC

FP_ROUND defaults to Legal for all MVT types and nothing changes
the v4f32 entry way from this d...

028764d8d611560a9bb1fbff500d5c0bd0ca801f authored over 5 years ago by Craig Topper <[email protected]>
Revert [SROA] Enhance SROA to handle `addrspacecast`ed allocas

This reverts r363711 (git commit 76a149ef8187310a60fd20481fdb2a10c8ba968e)

This causes stage2 b...

ec8c65256886edf88bfd3234b16c370b7432592a authored over 5 years ago by Jordan Rupprecht <[email protected]>
[TargetLowering] SimplifyDemandedBits - Cleanup ANY_EXTEND handling

Match SIGN_EXTEND + ZERO_EXTEND handling - will be adding ANY_EXTEND_VECTOR_INREG support in a f...

08f0ec731b8b0f89bc646f3028b799ab49272a74 authored over 5 years ago by Simon Pilgrim <[email protected]>
[TargetLowering] SimplifyDemandedBits - Merge ZERO_EXTEND+ZERO_EXTEND_VECTOR_INREG handling

Other than adding consistent demanded elts handling which was a trivial addition, the other diff...

d26889bb0fffb3c2ce5929f3b1d4a99e0b35ba47 authored over 5 years ago by Simon Pilgrim <[email protected]>
[SROA] Enhance SROA to handle `addrspacecast`ed allocas

Summary:
- After `addrspacecast` is allowed to be eliminated in SROA, the
adjusting of storage...

3709f6b81ea8e94f6a6b26d015d9216c9435edce authored over 5 years ago by Michael Liao <[email protected]>
[TargetLowering] SimplifyDemandedBits - Merge SIGN_EXTEND+SIGN_EXTEND_VECTOR_INREG handling

Other than adding consistent demanded elts handling which was a trivial addition, the other diff...

0e6f40003765dc305f54dc16acd33453e605c5a6 authored over 5 years ago by Simon Pilgrim <[email protected]>
[CodeGen] Fix Mips and SystemZ fast-isel tests

Missed a few tests in the previous commit.

2238e5157785fa7185dd39ece566889c073f9516 authored over 5 years ago by Francis Visoiu Mistrih <[email protected]>
[x86] add test for load splitting with extracted store (PR42305); NFC

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363704 91177308-0d34-0410-b5e6-96231b3b...

2240b8915a6d70cb2284dd6ac167800acff152c8 authored over 5 years ago by Sanjay Patel <[email protected]>
[mips] Add more strict predicates to the RSQRT_S_MM and TAILCALL_MM

This patch is one of a series of patches. The goal is to make P5600
scheduler model complete and...

a0dfa7717fba0de8701aa9916f7d6f76f60b4434 authored over 5 years ago by Simon Atanasyan <[email protected]>
[mips] Add PTR_64 and GPR_64 predicates to some MIPS 64-bit instructions

Add `IsGP64bit` and `IsPTR64bit` to the list of `UnsupportedFeatures`
of the P5600 scheduling de...

ec7242b85c349e1d85a4f4c6a962f22e82b98d30 authored over 5 years ago by Simon Atanasyan <[email protected]>
[mips] Set the hasNoSchedulingInfo flag for the `MipsAsmPseudoInst`

Set the hasNoSchedulingInfo flag for the`MipsAsmPseudoInst`. These
pseudo-instructions are never...

f8f8ebdf9545b21815d6b9e362453f315f04526d authored over 5 years ago by Simon Atanasyan <[email protected]>
Fix some lit test ResourceWarnings on Windows

When running LLDB lit tests on Windows, the system selects a debug version
of Python, which was ...

2e02d2b3a348b0775083a092aaae46df8c779f3d authored over 5 years ago by Adrian McCarthy <[email protected]>
[ARM] Add MVE vector shift instructions.

This includes saturating and non-saturating shifts, both with
immediate shift count and with the...

51481b9bae5b4f293070afa9f987df3c5c0566e8 authored over 5 years ago by Simon Tatham <[email protected]>
[ARM] Add MVE integer vector min/max instructions.

Summary:
These form a small family of their own, to go with the floating-point
VMINNM/VMAXNM ins...

636a9042976fb6564cfbd9eab1c30d82fe473718 authored over 5 years ago by Simon Tatham <[email protected]>
[TargetLowering] SimplifyDemandedVectorElts - support MUL and ANY_EXTEND_VECTOR_INREG

Also fold ANY_EXTEND_VECTOR_INREG -> BITCAST if we only need the bottom element.

Fixes temporar...

ddc701aa7ff7aebe8ec5aaa914fff3c9589a52fb authored over 5 years ago by Simon Pilgrim <[email protected]>
[X86][AVX] extract_subvector(any_extend(x)) -> any_extend_vector_inreg(x)

Part of fixing the X86 regression noted in D63281 - I've split this into X86 and generic parts -...

fb0ede3c0ca4c5ba95af65fac5d3b9e20e21a196 authored over 5 years ago by Simon Pilgrim <[email protected]>
[ARM] Rename MVE instructions in Tablegen for consistency.

Summary:
Their names began with a mishmash of `MVE_`, `t2` and no prefix at
all. Now they all st...

d3eebe830583645f79dae1c0911cbf47f70deeb2 authored over 5 years ago by Simon Tatham <[email protected]>
Merge remote-tracking branch 'llvm.org/master' into upstream-with-swift

Conflicts:
include/llvm/ADT/DenseMapInfo.h

eaa2efc482e3d62fc8fa3a0bc9a2692c725b63db authored over 5 years ago by Florian Hahn <[email protected]>
Merge remote-tracking branch 'origin/swift-5.1-branch' into stable

45f228e50b6fbb16c7a8d6703df8e87433a6a18d authored over 5 years ago by swift_jenkins <[email protected]>
[RISCV] Lower calls through PLT

This patch adds support for generating calls through the procedure
linkage table where required ...

f528f0e60898197fde2faf503c36abad5e033dd8 authored over 5 years ago by Lewis Revill <[email protected]>
Fix -Wunused-but-set-variable warning. NFCI.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363685 91177308-0d34-0410-b5e6-96231b3b...

453ecb9e1b01e4fdb27380a3de1d6e406ad42b47 authored over 5 years ago by Simon Pilgrim <[email protected]>
[llvm-readobj] Allow --hex-dump/--string-dump to dump multiple sections

1) `-x foo` currently dumps one `foo`. This change makes it dump all `foo`.
2) `-x foo -x foo` c...

894e54f898f9bfc48f82b987b09d1dd02e174054 authored over 5 years ago by Fangrui Song <[email protected]>
AMDGPU: Add ds_gws_init / ds_gws_barrier intrinsics

There may or may not be additional work to handle this correctly on
SI/CI.

git-svn-id: https://...

6a59b73682654043e0be54ba181cfed4afdb5147 authored over 5 years ago by Matt Arsenault <[email protected]>
[MCA] Slightly refactor the bottleneck analysis view. NFCI

This patch slightly refactors data structures internally used by the bottleneck
analysis to trac...

919946cec1b59c04d977927bd4185a19d8b05598 authored over 5 years ago by Andrea Di Biagio <[email protected]>
AMDGPU: Change API for checking for exec modification

Invert the name and return value to better reflect the imprecise
nature.

Force passing in the D...

9f1f314a53ce533e753396f77731ff89f9943bdd authored over 5 years ago by Matt Arsenault <[email protected]>
MCContext: Delete unused functions

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363674 91177308-0d34-0410-b5e6-96231b3b...

9ae5f77fd27dc9d5bb35364fd970fc2d63099209 authored over 5 years ago by Fangrui Song <[email protected]>
gn build: Merge r363658

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363673 91177308-0d34-0410-b5e6-96231b3b...

6ba6c1c9af6c8a45c774dcd6779262a81d562259 authored over 5 years ago by Nico Weber <[email protected]>
gn build: Merge r363649

This reverts commit "gn build: Merge r363626" because r363626
was reverted in r363649.

git-svn-...

9ad1ee6fd3e62e201f9c9b636d26628880489f2f authored over 5 years ago by Nico Weber <[email protected]>
[SelectionDAG] Legalize vaargs that require vector splitting

This adds vector splitting for vaarg instructions during type legalization

Committed on behalf ...

b9ec7f898ec478e1e51a5369c6fabad73670e7c3 authored over 5 years ago by Simon Pilgrim <[email protected]>
AMDGPU: Fold readlane from copy of SGPR or imm

These may be inserted to assert uniformity somewhere.

git-svn-id: https://llvm.org/svn/llvm-pro...

ccd9c0a5d7fad52578e3ef1bcd8ab77a5cc08f38 authored over 5 years ago by Matt Arsenault <[email protected]>
AMDGPU: Remove unnecessary check for virtual register

The copy was found by searching the uses of a virtual register, so
it's already known to be virt...

09e40fba68225661fb713c5ecc503b318dbe23ba authored over 5 years ago by Matt Arsenault <[email protected]>
AMDGPU: Fix iterator crash in AMDGPUPromoteAlloca

The lifetime intrinsic was erased, which was the next iterator.

git-svn-id: https://llvm.org/sv...

882e36914312275d58d5bb483acb475c0b62b014 authored over 5 years ago by Matt Arsenault <[email protected]>
AMDGPU/GlobalISel: RegBankSelect for amdgcn.div.scale

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363667 91177308-0d34-0410-b5e6-96231b3b...

4f2ff6f3f771d2d788e545bf6e1cb086e447bbe3 authored over 5 years ago by Matt Arsenault <[email protected]>
[ARM] Some Thumb2ITBlock clean ups. NFC

Some more refactoring, like registering the IT Block pass, less cryptic
variable names, and some...

ea7454bc0696023d85825b528b56b786a393a704 authored over 5 years ago by Sjoerd Meijer <[email protected]>
[SystemZ] Fix AHIMuxK pseudo expansion.

Do not emit a copy if the source and destination registers are the same.

Review: Ulrich Weigand...

066bfdcdb8ae335ea2d8a492f07d2cdacc2dade0 authored over 5 years ago by Jonas Paulsson <[email protected]>
[AMDGPU] Speed up live-in virtual register set computaion in GCNScheduleDAGMILive.

Differential revision: https://reviews.llvm.org/D62401

git-svn-id: https://llvm.org/svn/llvm-pr...

b0b4bb7b62a71446183f1179542a0489f32b7e51 authored over 5 years ago by Valery Pykhtin <[email protected]>
[SVE][IR] Scalable Vector IR Type with pr42210 fix

Recommit of D32530 with a few small changes:
- Stopped recursively walking through aggregates ...

3ec873e4ef38cb98227a6bdd4ea812d616dd33ce authored over 5 years ago by Graham Hunter <[email protected]>
[X86] Regenerate promote.ll. NFC.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363657 91177308-0d34-0410-b5e6-96231b3b...

dae6fcf9b436f0e602725f585e2b43ac069a4b59 authored over 5 years ago by Simon Pilgrim <[email protected]>
Propagating prior merge from 'llvm.org/master'.

b70159e43020dc9b1bf05b03b2bc5a4097de566d authored over 5 years ago by Automerger <Automerger@Swift>
[NFC] Improve triple match of scripts that update tests

Summary:
The prior behavior of the triple matcher would stop
in the first matched triple. It was...

5dae52e84b3fcdceabe47f67cfaf7269f7ccea10 authored over 5 years ago by Diogo N. Sampaio <[email protected]>
Propagating prior merge from 'llvm.org/master'.

ea62268aa2980e493fb0dff77e831fa456e3eb47 authored over 5 years ago by Automerger <Automerger@Swift>
[X86] Replace any_extend* vector extensions with zero_extend* equivalents

First step toward addressing the vector-reduce-mul-widen.ll regression in D63281 - we should rep...

71363c5318de58dff9abefdfc5ae0ddd0f08b4fc authored over 5 years ago by Simon Pilgrim <[email protected]>
[DebugInfo][Docs] Document that prologue/epilogue variable location changes are ignored

This patch documents that LLVM does not describe all changes in variable
locations during the pr...

d65677457c49ce6b6afd3a287793b59b56a9b20e authored over 5 years ago by Jeremy Morse <[email protected]>
Propagating prior merge from 'llvm.org/master'.

ab5f243683d35590df930e96b6116dc8a1832900 authored over 5 years ago by Automerger <Automerger@Swift>
[SimplifyCFG] NFC, prof branch_weighs handling is simplified

Using the new SwitchInstProfUpdateWrapper this patch
simplifies 3 places of prof branch_weights ...

71cd3ded124033b1ed84a9c19b08e9f638d41011 authored over 5 years ago by Yevgeny Rouban <[email protected]>
[llvm-objdump] Tidy up AMDGCNPrettyPrinter

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363650 91177308-0d34-0410-b5e6-96231b3b...

0ef6742182ddae5ebb117b16a1e2724157053d1f authored over 5 years ago by Fangrui Song <[email protected]>
[X86] Add i128 ctpop and i32/i64/i128 optsize test cases to popcnt.ll

Test cases for PR41151 and D59909.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363...

0a388ab41617a350e3adcb17a74302bb44b71641 authored over 5 years ago by Craig Topper <[email protected]>
[X86] Move code that shrinks immediates for ((x << C1) op C2) into a helper function. NFCI

Preliminary step for D59909

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363645 911...

cb10396a25cfc97dc6fe82a817d2706368661edc authored over 5 years ago by Craig Topper <[email protected]>
[X86] Remove MOVDI2SSrm/MOV64toSDrm/MOVSS2DImr/MOVSDto64mr CodeGenOnly instructions.

The isel patterns for these use a bitcast and load/store, but
DAG combine should have canonicali...

f76266ec02c978a36023f6e9363da36e338fae30 authored over 5 years ago by Craig Topper <[email protected]>
[X86] Introduce new MOVSSrm/MOVSDrm opcodes that use VR128 register class.

Rename the old versions that use FR32/FR64 to MOVSSrm_alt/MOVSDrm_alt.

Use the new versions in ...

c59023cdb5bb3780bb5076c3687c66b3388a8be6 authored over 5 years ago by Craig Topper <[email protected]>
GlobalISel: Remove redundant pass initialization

Summary:
All the GlobalISel passes are initialized when the target calls
initializeGlobalISel(),...

651c7e1f87cb9abe0671d77636dd6e082deec9b1 authored over 5 years ago by Tom Stellard <[email protected]>
[llvm-strip] Error when using stdin twice

Summary: Implements bug [[ https://bugs.llvm.org/show_bug.cgi?id=42204 | 42204 ]]. llvm-strip no...

1a8c6875ab900c940188a350c1cfaff848407e42 authored over 5 years ago by Alex Brachet <[email protected]>
GlobalISel: Use the original flags when lowering fneg to fsub

This was ignoring the flag on fneg, and using the source instruction's
flags. Also fixes tests m...

e14caa73dc2848435b88cd931cb6ed8449951dba authored over 5 years ago by Matt Arsenault <[email protected]>
hwasan: Use bits [3..11) of the ring buffer entry address as the base stack tag.

This saves roughly 32 bytes of instructions per function with stack objects
and causes us to pre...

644422a4d3f3afaeec80f0183065af9cb894411d authored over 5 years ago by Peter Collingbourne <[email protected]>
hwasan: Add a tag_offset DWARF attribute to instrumented stack variables.

The goal is to improve hwasan's error reporting for stack use-after-return by
recording enough i...

f159a1182eabe15e1f6dcd9512bf47be5c8a0c66 authored over 5 years ago by Peter Collingbourne <[email protected]>
gn build: Merge r363626.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363634 91177308-0d34-0410-b5e6-96231b3b...

bca91c8cabcaa21851f4eb67d4fe6cb36055d468 authored over 5 years ago by Peter Collingbourne <[email protected]>
[GlobalISel][Localizer] Rewrite localizer to run in 2 phases, inter & intra block.

Inter-block localization is the same as what currently happens, except now it
only runs on the e...

f765312a6fada38a914163b8eb85daa52daf0b67 authored over 5 years ago by Amara Emerson <[email protected]>
Propagate fmf in IRTranslate for fneg

Summary: This case is related to D63405 in that we need to be propagating FMF on negates.

Revie...

95009014f826bf03040de3348e30b85010329e46 authored over 5 years ago by Michael Berg <[email protected]>
Propagating prior merge from 'llvm.org/master'.

2e2f2841a90f299e5ec16a1e962a1992dcc02acd authored over 5 years ago by Automerger <Automerger@Swift>
Use VR128X instead of FR32X/FR64X for the register class in VMOVSSZmrk/VMOVSDZmrk.

Removes COPY_TO_REGCLASS from some patterns.

git-svn-id: https://llvm.org/svn/llvm-project/llvm...

8d008c0fb8a0c155ab00b74c712379f1e564a6f0 authored over 5 years ago by Craig Topper <[email protected]>
[X86] Make an assert in LowerSCALAR_TO_VECTOR stricter to make it clear what types are allowed here. NFC

Make it clear that only integer type with i32 or smaller elements shoudl get to this part of the...

300b39cdac57e0ab8009eaead62af9f8b3671fa6 authored over 5 years ago by Craig Topper <[email protected]>
[AMDGPU] Use custom inserter for gfx10 VOP2b

This is part of the approved D63204 pending parent revision.
This small change is in fact a part...

37e080d8710e88832a169e4adf806292f1ecbed2 authored over 5 years ago by Stanislav Mekhanoshin <[email protected]>
[AMDGPU] gfx1010 subvector test. NFC.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363623 91177308-0d34-0410-b5e6-96231b3b...

4b0f16838aa8a217c7865d7edc3c45b66821bfd1 authored over 5 years ago by Stanislav Mekhanoshin <[email protected]>
[test][AArch64] Relax the check line for G_BRJT in legalizer-info-validation.mir

Replace the specific number with a pattern to relax the test.

git-svn-id: https://llvm.org/svn/...

a313274b56056b6e8f2edd7a5e8060c64538f83b authored over 5 years ago by Volkan Keles <[email protected]>