When an instruction doesn't have a valid encoding for the target ISA, it
needs to be legalized. ...

The encoding tables contain references to numbered ISA predicates.

- Give the ISA Flags types a...

When a hash table probe fails, return the index of the failed entry.
This can be used to store d...

band, bor, bxor, band_not are all available on XMM registers.

ARM has all of these as scalar integer instructions. Intel has band_not
in SSE and as a scalar i...

These map to single Intel instructions.

The i64 to float conversions are not tested yet. The en...

Use a ud2 instruction which generates an undefined instruction
exception.

This conversion doesn't require any code, we're just looking at the bits
differently.

This only works on 64-bit haswell for now. We need more legalization
patterns for 32-bit ISAs.

One function for each comparison operator.

Convert b1 to i32 or i64 by zero-extending the byte.

This instruction returns a `b1` value which is represented as the output
of a setCC instruction ...

A fallthrough jump is actually represented as 0 bytes, so no encoding is
needed.

Also allow for...

Just implement jump, brz, and brnz as needed for WebAssembly.

Register locations can change throughout an EBB. Make sure the
emit_inst() function considers th...

Add instructions representing Intel's division instructions which use a
numerator that is twice ...

This function will emit the binary machine code into contiguous raw
memory while sending relocat...

Fixes #11.

Presets are groups of settings and values applied at once. This is used
as a shortha...

This makes the documentation for the new bconst instruction more complete.

During register allocation, the code must be kept in conventional SSA
form. Add a verifier that ...

* Add a bconst instruction.

Guard the popcnt instruction on the proper CPUID bits.

Change the result type for the bit-counting instructions from a fixed i8
to the iB type variable...

Start adding little 'test compile' test cases which check that the full
compilation pipeline wor...

This is the main entry point to the code generator. It returns the
computed size of the function...

Cretonne allows '_' in number constants.

This instruction moves a value between registers. This counts as a side
effect that is not track...

All emitted regmove instructions must be materialized as real move
instructions.

Same as a register copy, but different arguments.

Include ISA-specific annotations in tracing and error messages.

When the test driver reports a verifier error, make sure to include the
TargetIsa when printing ...

We allow ghost instructions to exist if they have no side effects.
Instructions that affect cont...

This is used to indicate instructions that have some side effect that is
not modelled by the mor...

* Reduce code duplication in TypeConstraint subclasses; Add ConstrainWiderOrEqual to ti and to i...

* API and data structures proposal for the SSA construction module

* Polished API and impleme...

Use a PUT_OP macro in the TailRecipe Python class to replace the code
snippet that emits the pre...

Add a TailRecipe.rex() method which creates an encoding recipe with a
REX prefix.

Define I64 en...

* Emit runtime type checks in legalizer.rs

Generate code to:

- Unwrap the instruction and generate an error if the instruction format
do...

Write out multiple code lines from a single string after stripping a
common indentation.

Also u...

The redefined tied value lives in the diverted register.

Many ISAs don't need 4 top-level register classes, so don't print them.

Any tied register uses are interesting enough to be added to the reguses
list if their value is ...

As per the comment in TypeEnv.normalize_tv about cancellation, whenever we create a TypeVar we m...

We need to move the previous value out of the way first.

Also add a display() method which accepts a RegInfo reference.

Make sure we use the diverted register location for tied operands.

* Add more rigorous type inference and encapsulate the type inferece code in its own file (ti.py...

* Fixed bug in verifier
Does not check variable def for unreachable codex

* Check reachabili...

Include a very basic test using an Intel 'sub' instruction. More to
follow.

This is just a rough sketch to get us started. There are bound to be
some issues.

This also leg...

It is sometimes useful to create constant lists of register units by
name. The generated RU enum...

Tests are forthcoming, we need to implement Intel ABI lowering first.

The following constraints may need to be resolved during spilling
because the resolution increas...

Use it to access live ranges that are supposed to be there.

It is possible to pass a register value as an argument to an EBB that
expects a "None" affinity....

We'll need to pick a spill candidate from a set and allow for the search
to fail to find anythin...

A priory, an EBB argument value only gets an affinity if it is used
directly by a non-ghost inst...

When an EBB argument value is used only as a return value, it still
needs to be given a register...

A function parameter in an incoming_arg stack slot should not be
coalesced into any virtual regi...

Function arguments that don't fit in registers are passed on the stack.

Create "incoming_arg" s...

The offset is relative to the stack pointer in the calling function, so
it excludes the return a...

When coloring registers for a branch instruction, also make sure that
the values passed as EBB a...

Ghost instructions don't generate code, but they can keep registers
alive. The coloring pass nee...

When the spiller decides to spill a value, bring along all of the values
in its virtual register...

* Convert TypeSet fields to sets; Add BitSet<T> type to rust; Encode ValueTypeSets using BitSet;...

Coalescing means creating virtual registers and transforming the code
into conventional SSA form...

Add a VirtRegs collection which tracks virtual registers.

A virtual register is a set of relate...

The overlaps_def() method tests if a definition would conflict with the
live range.

The reaches...

Ghost instructions don't have an encoding, and don't appear in the
output. The values they defin...

For large constants with the low 12 bits clear, we already have the
"lui" encoding. Add "addi %x...

* Clarify that extended basic blocks are abbreviated as EBB.

* Fix typo.

* Fix a typo.

...

The EntityRef trait is used by more than just the EntityMap now, so it
should live in its own mo...

* Replace a single-character string literal with a character literal.

* Use is_some() instead...

* Implement an iterator over encodings

* Implement TargetIsa::legal_encodings

* Exclude no...

As soon as a value is spilled, also assign it to a spill slot.

For now, create a new spill slot...